Off-chip ESD protection anticipates IC scaling
Keywords: off-chip ESD protection transient voltage suppression clamping voltage submicron ICs
[Summary of tips] As next-generation transceivers and digital communications ICs scale to smaller geometries, the challenge for IC manufacturers to maintain reasonable levels of on-chip ESD protection becomes greater. Proposed decreases in on-chip ESD protection mean that system designers must be more aware of building ESD protection into their ......|
Registered already? Login to view complete content.
|

All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.

















