FPGAs/PLDs 
Synthesizable CIO DDR RLDRAM II controller for Virtex-4 FPGAs
Keywords: Virtex-4 Common I/O DDR RLDRAM II Xilinx
[Summary of tips] This application note describes how to use a Virtex-4 device to interface to Common I/O (CIO) Double Data Rate (DDR) Reduced Latency DRAM (RLDRAM II) devices. The reference design targets two CIO DDR RLDRAM II devices at a clock rate of 200/235 MHz with data transfers at 400/470Mbps per pin.View the PDF document for more inform......Please login or register with us to view this article>>
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