EDA/IP 
Asynchronous interconnects need innovative tools
Keywords: EDA tools EDA vendor self-timed circuits asynchronous interconnect for complex chips innovate or vacate
[Summary of tips] Fritz: There is no fundamental reason that additional non-timing-based constraints cannot be added to existing tools.Take a cursory look at the SoCs on the drawing board. You'll see some common problems stemming from design requirements that encompass dozens of intellectual-property cores, very high-speed clocks, multiple clock......Please login or register with us to view this article>>
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