EDA/IP 
EDA 'troublemakers' debate at DVCon
Keywords: CPF IC design IC design verification design verification low power standard
[Summary of tips] The annual "EDA Bigwigs" panel at the Design and Verification Conference (DVCon) was renamed the "Troublemaker's Panel" this year for good reason. Confronted with provocative questions, EDA vendor representatives debated such topics as low-power standards, Cadence Design Systems' Skill language, and outsourcing to India.As in p......Please login or register with us to view this article>>
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