Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011     MCU     MEMS     IGBT     processor     LED     RFID
EE Times-Asia > EDA/IP
 
 
EDA/IP  

Design RFICs with greater speed, accuracy

Posted: 16 Nov 2006  Print Version  Bookmark and Share Subscribe

Keywords: RFIC  mobile communication systems  DSP  front-end  RF Design Methodology Kit 

[Summary of tips] In RFIC design, a "meet-in-the-middle" approach balances top-down fast design processes with bottom-up silicon accuracy to produce a predictable schedule, leading to first-pass silicon success.View the PDF document for more information.
 

votes:   Add to Favorites
Design for balun integration in RF L...
Homogenization eases FEM simulation
Article Comments - Design RFICs with greater speed, acc...
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
    Kindle Fire Hot CE innovations at the CES

    All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.

Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top