EDA/IP 
Plan early to reduce IC power usage
Keywords: Eike Schmidt ChipVision ic power consumption cmos logic
[Summary of tips] Historically, area and performance have been the key drivers for IC design. But increasingly, power minimization has become the key objective, with more and more designs failing or having to be respun due to power issues. Consequently, a consistent methodology for low-power design is required right from the start of the design,......Please login or register with us to view this article>>
|
Not yet registered?
 Register FREE to view unlimited features, tutorials and products, and enable any content alert service! |
Registered already? Login to view complete content.
|
Article Comments - Plan early to reduce IC power usage
Visitor0530
(To avoid code verification, simply login or register with us. It is fast and free!)
Search EE Times Asia
Peek at Hot Gadgets for 2012
