Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011     MCU     MEMS     IGBT     processor     LED     RFID
EE Times-Asia > EDA/IP
 
 
EDA/IP  

Build efficient datapath designs

Posted: 03 Oct 2005  Print Version  Bookmark and Share Subscribe

Keywords: synopsys  datapath  synthesis  compiler  arithmetic logic 

[Summary of tips] This article proposes RTL coding guidelines and a context-sensitive RTL datapath synthesis for improving design productivityView the PDF document for more information.
 

votes:   Add to Favorites
Design Trends and EDA Tools: China &...
Developing macrocell libraries in CM...
Article Comments - Build efficient datapath designs
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
    Kindle Fire Hot CE innovations at the CES

    All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.

Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top