Processors/DSPs 
Timing analyzer puts ASIC-like functionality in FPGAs
Keywords: actel timing analysis libero integrated design environment ide
[Summary of tips] BROKEN_TABLE_ HIDDEN_END -->Claiming new functionality along with ease of use, Actel Corp. recently rolled out a static timing analysis engine as part of the Libero 6.2 integrated design environment (IDE) for Actel fpgas. The release also strengthens third-party tool support.Libero 6.2 features smarttime, a new static timing a......Please login or register with us to view this article>>
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