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Synopsys test methodologies verify SLE's chip developments
Keywords: rtl verification solution vera testbench automation tool asic design silicon logic engineering
[Summary of tips] BROKEN_TABLE_ HIDDEN_END -->Synopsys Inc. announced that its VCS comprehensive RTL verification solution and Vera testbench automation tool have been adopted by ASIC design services provider Silicon Logic Engineering (SLE) to accelerate its chip development process.SLE is apparently taking advantage of the Synopsys reference v......Please login or register with us to view this article>>
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