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EDA/IP  

Latency analysis of major chip-to-chip interconnects

Posted: 16 Feb 2005  Print Version  Bookmark and Share Subscribe

Keywords: chip-to-chip  interconnect  latency  rapidio  hypertransport 

[Summary of tips] Compare and contrast the latency experienced by transactions carried over several of the leading chip-to-chip interconnect standards.View the PDF document for more information.
 

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