EDA/IP 
Placement tools criticized for hampering IC designs
Keywords: ic placement algorithm chip design ucla eda tool
[Summary of tips] Current IC placement algorithms leave so much excess wire that chip designs are essentially several technology generations behind where they could be, according to a recent paper by researchers at the University of California at Los Angeles (UCLA). EDA vendors have responded by stating that commercial placement tools are not as......Please login or register with us to view this article>>
|
Not yet registered?
 Register FREE to view unlimited features, tutorials and products, and enable any content alert service! |
Registered already? Login to view complete content.
|
Article Comments - Placement tools criticized for hampe...
Visitor0213
(To avoid code verification, simply login or register with us. It is fast and free!)
Top Ranked Articles
Christmas Wishlist
All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.
Search EE Times Asia
Peek at Hot Gadgets for 2012
