EDA/IP 
'Infrastructure IP' seen aiding SoC yields
Keywords: SoC semiconductor Design Automation Conference Agere IP core
[Summary of tips] Design-for-yield is becoming a goal for system-on-chip (SoC) designers as today's very deep-submicron semiconductor technologies of 130 nanometers and below are reaching defect susceptibility levels that result in lower manufacturing yields and reliability. Papers from Agere Systems Inc. and Virage Logic Corp. at the 39th Desig......Please login or register with us to view this article>>
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