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Inductance analysis of chip scale packages

Posted: 19 Jun 2001  Print Version  Bookmark and Share Subscribe

Keywords: bogatin  chip scale package  csp  package  inductance 

[Summary of tips] This application note is intended to demonstrate a simple model that relates the maximum operating clock frequency of a CSP based on the IC's power dissipation, the typical lead equivalent inductance and the number of pairs of leads used for power and ground.View the PDF document for more information.
 

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