FPGAs/PLDs 
EDA Consortium tackles FPGA productivity
Keywords: eda hdl edac asic fpga
[Summary of tips] BROKEN_TABLE_ HIDDEN_END -->Design organizations can leap to increase productivity, according to panelists at the EDA Consortium (EDAC) meeting held in San Jose, California. Panelists each called for direct HDL entry, design reuse and better productivity measurements.Tom Pennino, director of CAD systems at Lucent Technologies,......Please login or register with us to view this article>>
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