Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011     MCU     MEMS     IGBT     processor     LED     RFID
EE Times-Asia > EDA/IP
 
 
EDA/IP  

Co-verification speeded up for design

Posted: 16 Jun 2001  Print Version  Bookmark and Share Subscribe

Keywords: ipc  verification  vcpu  gui  xcite 

[Summary of tips] BROKEN_TABLE_ HIDDEN_END -->Innoveda Inc. boosted the performance of its V-CPU hardware/software co-verification system through a link with Axis Systems' simulation accelerator and emulator.The latest spin of V-CPU, version 4.0, formally integrates Xcite and xtreme, Axis' simulation accelerator and emulator, said Steve Anderso......
Please login or register with us to view this article>>
 

votes:   Add to Favorites
Two mysteries of PCB thermal analysi...
3D design tools for package flexibil...
Article Comments - Co-verification speeded up for desig...
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
    Kindle Fire Hot CE innovations at the CES

    All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.

Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top