Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011     MCU     MEMS     IGBT     processor     LED     RFID
EE Times-Asia > EDA/IP
 
 
EDA/IP  

Guidelines for supplying test vector simulations

Posted: 23 Apr 2001  Print Version  Bookmark and Share Subscribe

Keywords: ami  test vector simulation  asic  ic simulation  simulation tool 

[Summary of tips] This application note provides the necessary information to ensure that the vectors generated from the functional verification and testing of an ASIC will fit within AMI's standard test format.View the PDF document for more information.
 

votes:   Add to Favorites
Synthesizing LSS designs with Synops...
Using NAND tree test circuits for in...
Article Comments - Guidelines for supplying test vector...
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
    Kindle Fire Hot CE innovations at the CES

    All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.

Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top