Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011     MCU     MEMS     IGBT     processor     LED     RFID
EE Times-Asia > EDA/IP
 
 
EDA/IP  

Timing analysis tools greatly impacts a successful design

Posted: 01 May 2001  Print Version  Bookmark and Share Subscribe

Keywords: asic  fpga  board simulation  pvt  dcl 

[Summary of tips] Today, static timing analysis tools have matured to the point of handling significantly more complex design styles. This article examines the different kinds of timing analysis products used in ASIC, FPGA, and board-level design.View the PDF document for more information.
 

votes:   Add to Favorites
Putting automated libraries into the...
Taiwan takes stocks
Article Comments - Timing analysis tools greatly impact...
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
    Kindle Fire Hot CE innovations at the CES

    All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.

Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top