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EDA/IP  

Hierarchical physical design for million-gate ASICs

Posted: 15 Apr 2001  Print Version  Bookmark and Share Subscribe

Keywords: asic  floorplan tool  formal verification  cad  vdsm 

[Summary of tips] Raw design size in million-gated ASICs can cripple physical design and timing closure and the viable solution is physical hierarchy.View the PDF document for more information.
 

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