T&M 
Timing closure in DSM design
Keywords: sta circuit verification asic simulation rc interconnect
[Summary of tips] Timing closure has taken center stage as the toughest challenge for today's deep-submicron designs. Subsequently, the problem of accurate timing verification has become more important than ever before. Can engineers continue to predict the timing of ICs prior to manufacturing as technologies continue to scale?View the PDF docum......Please login or register with us to view this article>>
|
Not yet registered?
 Register FREE to view unlimited features, tutorials and products, and enable any content alert service! |
Registered already? Login to view complete content.
|
Article Comments - Timing closure in DSM design
Visitor0213
(To avoid code verification, simply login or register with us. It is fast and free!)
Top Ranked Articles
Christmas Wishlist
All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.
Search EE Times Asia
Peek at Hot Gadgets for 2012
