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Manufacturing/Packaging  

Testing dimensional limits of high I/O flip-chip design

Posted: 01 Feb 2001  Print Version  Bookmark and Share Subscribe

Keywords: flip-chip  fea  cte  microintegration  solder bridge 

[Summary of tips] The study characterizes underfill materials, examining some large package geometries and design manufacturing processes to avoid defects for I/O counts.View the PDF document for more information.
 

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