Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011   MCU   MEMS   IGBT   processor   LED   RFID
EE Times-Asia > FPGAs/PLDs
 
 
FPGAs/PLDs  

EDA platform benchmark: The desktop FPGA design flow

Posted: 01 Jan 2001  Print Version  Bookmark and Share Subscribe

Keywords: fpga  eda benchmark  asic design  scsl  verilog 

[Summary of tips] This article evaluates the system requirements of your desktop against typical FPGA designs you would encounter.View the PDF document for more information.
 

votes:   Add to Favorites
A New Way To Design ASICs
Soft radios and modems on FPGAs
Article Comments - EDA platform benchmark: The desktop ...
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top