Global Sources
EE Times-Asia
Advanced Search
News
Products
Technical Articles
App Notes
ForumBlogsWhite PapersDatasheetsWebinars
 Challenges & Opportunities 2011   MCU   MEMS   IGBT   processor   LED   RFID
EE Times-Asia > FPGAs/PLDs
 
 
FPGAs/PLDs  

16-bit up/down counter/shift register

Posted: 01 Sep 2000  Print Version  Bookmark and Share Subscribe

Keywords: atmel  fpga  pga  gate array  programmable logic 

[Summary of tips] This application note demonstrates how to implement the AT6000 Series FPGA as a synchronous, 16-bit up/down counter/shift register that operates at 22MHz under the worst commercial operating conditions.View the PDF document for more information.
 

votes:   Add to Favorites
16-bit carry-select adder
Compact, loadable 16- and 32-bit bin...
Article Comments - 16-bit up/down counter/shift registe...
Comments:  
*  You can enter [0] more charecters.
*Verify code:
 
Top Ranked Articles
High-quality Articles
Christmas Wishlist
Search EE Times Asia
Peek at Hot Gadgets for 2012
Smart energy "Try explaining to your eight-year-old son that instead of an Xbox, you got him a Wi-Fi enabled smart energy thermostat to help minimize his energy consumption and carbon footprint..."
 

Go to top