EDA/IP 
Achieving SoC Timing Convergence
Keywords: system on a chip soc design iteration timing
[Summary of tips] Today's complex SoCs are plagued with problems of timing convergence. Use optimization tools in the layout phase, as well as new techniques to correct timing problems.View the PDF document for more information.|
Not yet registered?
 Register FREE to view unlimited features, tutorials and products, and enable any content alert service! |
Registered already? Login to view complete content.
|
Article Comments - Achieving SoC Timing Convergence
Visitor0213
(To avoid code verification, simply login or register with us. It is fast and free!)
Top Ranked Articles
Christmas Wishlist
All I want for Christmas is any of this year's Best of Innovations Design and Engineering Award honorees! Here's the EE Times pick for Top 10 CE gadgets.
Search EE Times Asia
Peek at Hot Gadgets for 2012
