| 2007-7-3 |
Signal integrity toolkit checks jitter, boasts new Serdes lib
Agilent has pulled the wraps off a new toolkit that identifies and analyzes sources of jitter in multi-gigabit communication link designs. |
| 2007-6-29 |
A new way to predict LDMOS DC signal behavior
To reduce the design cycle time and cost for wireless applications, it is useful to have models that can help predict and simulate the behavior of RF power transistors, such as ST's PD54003L-E device. |
| 2007-6-20 |
FPGA design kit achieves higher abstraction levels
Actel Corp. is rolling out SmartDesign, a graphical design entry capability that promises to bring FPGA design to a higher level of abstraction. |
| 2007-6-12 |
ARM to field verification IP for on-chip comms
ARM plc will start sampling to its lead partners the AMBA Adaptive Verification IP for on-chip communication during the third quarter. |
| 2007-6-1 |
Check interconnections between FPGAs on a high-density board
This article describes a simple, effective and generic solution to check signal connectivity between FPGAs on a high density prototyping board with multiple FPGAs and hundreds of signals. |
| 2007-6-1 |
Design with serial EEPROM devices
Available with varying capacities, interface protocols, voltages and temperature ranges, serial EEPROM units are used in applications running the gamut from automotive to medical and consumer goods. Here are some do's and don'ts for designing with serial EEPROM devices. |
| 2007-6-1 |
XA offers better simulation accuracy
Promising a new approach to fast Spice simulation, Synopsys Inc. introduced Discovery AMS 2007, a group of solutions that includes the XA simulation technology option for the NanoSim and HSim fast SPICE simulators. |
| 2007-5-28 |
Re-synthesis solution cuts 24% die area
California-based Nangate Inc. claims that its re-synthesis solution will provide digital IC designers with the advantages of full custom design implementation while preserving the benefits of cell-based design methodologies. |
| 2007-5-21 |
Register manager promises versatility
Electronic system-level (ESL) provider Duolog Technologies is set to roll out BitWise, a register manager that claims to accelerate SoC design. |
| 2007-5-18 |
Tool speeds up firmware debugging
Striving to meet the demands of firmware developers, Carbon Design Systems announced a new technology called "OnDemand" that speeds the performance of Carbon's Virtual System Prototype (VSP) environment for debugging. |
| 2007-4-9 |
Designing with serial E2PROM devices
Here are some do's and don'ts for designing with serial E2PROM devices. |
| 2007-4-2 |
65nm FPGAs set new DSP performance
Spreading its wings into new markets, Xilinx Inc. is shipping a line of high-end FPGAs that are optimized for high-performance DSP applications. |
| 2007-3-28 |
Tool taps clock gating for IC power optimization
Claiming breakthrough technology in IC power optimization, Calypto Design Systems is announcing PowerPro CG, a tool that automatically adds clock-gating logic to RTL code. |
| 2007-3-27 |
The dilemma of two languages in low-power design
EDA users may not like it, but when it comes to low-power design they will probably have to speak two languages: CPF and UPF. |
| 2007-3-15 |
IP embeds Bluetooth in consumer, auto ICs
For chip designers looking to embed Bluetooth in consumer and automotive ICs, CEVA is offering Bluetooth 2.0+EDR IP that gives them the flexibility in choosing the CPU, Bluetooth radio chipset and OS. |
| 2007-3-14 |
Co-verification solution rolls for Actel FPGAs
Aldec has announced the release of CoVer, a Windows-based HW/SW co-verification solution for Actel's ARM-based FPGAs. |
| 2007-2-21 |
SystemVerilog falls short for design
SystemVerilog is widely applied to verification, however, design use lags due to concerns about tool support. |
| 2007-2-16 |
Integrate 'hard' IP into an SoC
During the course of delivering such IP over the past several years, Impinj has witnessed a range of IP integration experiences¡ªfrom the painless to the nearly disastrous. Most of the pitfalls can be avoided by following a few recommendations. |
| 2007-2-1 |
Video processors roll for mobile handsets, PMPs
Claiming to have solved one of the "grand challenges" of video system design, Tensilica Inc. has introduced a family of software-based video processor engines for mobile handsets and personal media players. |
| 2007-1-24 |
Emulator handles 100 million gates at 20MHz
EVE SA has developed what it touts as the largest and fastest IC emulation product to date. ZeBu-XXL handles up to 100 million gates at up to 20MHz, and it supports both hardware and software verification. |
| 2007-1-16 |
New Bluesim supports virtual prototyping
Targeting an emerging niche within ESL design, Bluespec Inc. rolled out a new version of its Bluesim simulator that supports virtual prototyping for software development and hardware validation. |
| 2007-1-10 |
C-to-RTL compiler promises full-chip design
Startup CebaTech Inc. will roll out the C2R Compiler, a C-to-RTL compiler that promises to generate full-chip designs. |
| 2007-1-9 |
Verilog simulator offers faster RTL, gate-level simulation
SynaptiCAD has released VeriLogger Extreme, a compiled-code Verilog 2001 simulator, priced at $4,000 on Windows platforms. |
| 2007-1-1 |
Obtain best performance from your FPGA design
This article will explore how FPGA designers can benefit from the latest FPGA building blocks in their quest for higher system-level performance. |
| 2006-12-28 |
Video processor engines handle H.264
Tensilica announced a family of software-based video processor engines for mobile handsets and media players. |
| 2006-12-18 |
Perform full-chip verification for AMS ICs
Simulation during the design phase can be efficiently done using a top-down design methodology. |
| 2006-12-15 |
Mathworks adds signal integrity to RF Toolbox
Providing a signal-integrity analysis capability for broadband backplanes and PCB traces, The Mathworks is rolling out the RF Toolbox 2, which adds time-domain capabilities to this Matlab add-on package. |
| 2006-11-29 |
Virtual prototype support rolls out
Bluespec Inc. will roll out within the week a new version of its Bluesim simulator that supports virtual prototyping for software development and hardware validation. |
| 2006-11-16 |
Revised VHDL boosts IP security
The Accellera standards organization has approved a revised version of the VHDL specification, marking a huge step forward for the design language. |
| 2006-11-10 |
Xilinx upgrades XtremeDSP to support Virtex-5 LX, LXT
Xilinx Inc. has announced the immediate availability of version 8.2 of its XtremeDSP development tools, which feature optimized DSP support for Xilinx Virtex-5 LX and LXT |
| 2006-11-1 |
HDL Coder offers shortcut to IC design
The Mathworks Inc. offers the Simulink HDL Coder, which automatically generates synthesizable Verilog and VHDL from Simulink models and Stateflow diagrams. |
| 2006-10-30 |
Cadence, Source III partner for improved test validation
Cadence Design Systems Inc. and Source III Inc. entered a collaboration to enable improved test validation and faster test conversion for enhanced chip quality. |
| 2006-10-17 |
Aldec claims Verilog simulation speedup
Aldec's new Riviera-Pro 2006.10 HDL simulator promises to provide a 57 percent speedup for RTL simulation and a 250 percent speedup for gate-level and timing simulations over previous releases of the software. |
| 2006-10-16 |
Startups take on analog design automation
Automating analog IC design has proven to be a tough challenge, but two EDA startups are promising to do just that with a new "analog synthesis" technology. |
| 2006-10-16 |
Open-source tools ease C++ verification
Two engineers published a book on IC verification with C++ and launched a website with free open-source tools that can help IC verification teams. |
| 2006-10-10 |
Revised VHDL adds IP encryption capability
Proclaiming a major step forward for the VHDL design language, the Accellera standards organization this week announced it has approved a revised version of the VHDL specification, which features Property Specification Language (PSL) assertions and IP encryption capabilities. |
| 2006-10-4 |
Yogitech unveils 'first' Open Core Protocol UVC
Yogitech, a provider of design and verification technology, announced what it touts as the industry's first mixed-language Open Core Protocol universal verification component. |
| 2006-10-2 |
ESL solution prevents bug at source
MataiTech's Nauet is an ESL tool that lets hardware and software engineers collaborate at the earliest stages of a design, thus preventing bugs at the source. |
| 2006-9-18 |
Team of former ST engineers offers free 64bit processor
Simply RISC, a team of engineers formerly with STMicroelectronics, has produced its first offering, a 64bit processor codenamed Sirocco. |
| 2006-9-18 |
Spice tools rev speed, accuracy
Berkeley Design Automation released in August two products that claim to speed Spice simulation by five- to tenfold while preserving full Spice accuracy. |
| 2006-9-18 |
Simulation boosts FPGA-based DSP systems
The use of FPGAs as coprocessors provides considerable speed gains over high-end DSPs. The wide range of automated tools makes the development of FPGA-based DSP systems faster and easier than ever before. |
| 2006-9-18 |
Averant dives deep into formal verification
Averant took advantage of Design Automation Conference to roll out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification. |
| 2006-9-6 |
Website offers free open source C++ IC verification tools
Two engineers have launched a website with open-source tools that can help IC verification teams with C++ verification. |
| 2006-9-5 |
EDA tool offers OpenCores IP
MataiTech LLC has packaged OpenCores intellectual property (IP) with its fourth-generation EDA tool, Nauet 1.5. |
| 2006-9-1 |
Tool compiles C source code to RTL
CebaTech Inc. recently announced plans to offer both TCP/IP intellectual property (IP) and the C-language compiler that was used to create it. |
|
|
|
|
|
|Electronic Components|Computer Products|Trade Show Center|China Sourcing Fairs
|Site Feedback|Site Map|Help|About Us|Contact Us|Terms of Use|Privacy Policy|Security Commitment