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Formal Verification Tool news and hot articles

2007-6-18	Define your verification plan with SystemVerilog The adoption of constrained random testbenches, functional coverage and assertions fits seamlessly with embracing SystemVerilog. The value of these technologies is enhanced with an evolution of the verification planning process from simple test plans to VPA-driven verification plans.
2007-6-12	ARM to field verification IP for on-chip comms ARM plc will start sampling to its lead partners the AMBA Adaptive Verification IP for on-chip communication during the third quarter.
2007-6-8	EDA platform offers faster RF module design, verification Agilent now offers an EDA platform that provides a speedier design and verification process.
2007-5-3	Mentor, Anite partner on baseband SoC verification Anite is partnering with Mentor Graphics on a complete verification platform that will provide an integrated and efficient set up to verify baseband SoC designs.
2007-4-25	Device-native verification tool rolls for FPGAs Startup GateRocket has rolled out a device-native FPGA verification solution that includes hardware and software.
2007-4-2	Address verification issues with scalable methods This article examines how scalable verification, design for verification, and strategies that include abstraction, assertion-based techniques, and improved debugging methods address the fundamental challenges facing design teams.
2007-3-19	Plan your verification process with SystemVerilog The best way for the verification team to match the automatic tests with their corresponding design features is via functional coverage metrics.
2007-3-16	Manage verification with success Successful verification management requires good analysis of the specification, an awareness of the scope of the job at hand, and a firm decision on what coverage models and metrics to track. Here are some of the basic do's and don'ts to keep in mind.
2007-3-16	Take distinctive approach to IC verification Richard Goering spoke with Hooman Moshar about Broadcom's distinctive approach to IC verification.
2007-3-14	Co-verification solution rolls for Actel FPGAs Aldec has announced the release of CoVer, a Windows-based HW/SW co-verification solution for Actel's ARM-based FPGAs.
2007-2-23	C++ verification class library rolls for SystemC Filling what it sees as missing capabilities in the SystemC verification environment, Jeda Technologies is introducing NSCv, a C++ verification class library for SystemC.
2007-2-1	Accellera to define verification coverage metrics Responding to user calls for a consistent way to measure functional-verification completeness, the Accellera standards organization has launched the Unified Coverage Interoperability to define standards that enable the sharing and analysis of coverage data by different tools during the verification process.
2007-1-31	Verification box exceeds 200MHz speeds Gidel Ltd's Proc_SoC verification box claims to exceed verification speeds of 200MHz, thanks to a direct FPGA-to-FPGA interconnect scheme.
2007-1-15	Let metrics help with verification While the entire EDA industry is jumping on the coverage-driven bandwagon, clamoring for universal coverage databases and espousing the benefits of this "new" technology, one question arises. Are you making the most of all the metrics that are available to you today?
2007-1-10	Renesas adopts Synopsys' VCS verification solution Synopsys announced that Renesas has adopted the VCS functional verification solution and VMM methodology to verify its critical SuperHyway bus on-chip interconnect infrastructure.

2006-12-21	IC verification users satisfied, survey says Sixty percent of chip designers say they are satisfied with their IC verification environments according to a survey of more than 600 engineers sponsored by Emulation and Verification Engineering.
2006-12-20	eInfochips verification component supports Mentor's Questa A component that provides building blocks for efficient design-under-test in module and system-level verification for Mentor Graphics' Questa Vanguard program, including assertion testing, is now available from eInfochips Inc.
2006-12-18	Perform full-chip verification for AMS ICs Simulation during the design phase can be efficiently done using a top-down design methodology.
2006-12-6	Cadence India taps 13 new partners for verification alliance Thirteen companies have joined the Verification Alliance Program of Cadence Design Systems (India) Pte Ltd, a global partner network of consulting companies focused on verification consulting services, verification IP development and training for Cadence customers.
2006-11-22	Freescale, Synopsys ink verification agreement Freescale and Synopsys have signed an agreement for Freescale's use of the latter's electronic design automation software for the functional verification of complex semiconductor designs.
2006-10-26	S2 launches enhanced STRIDE verification platform S2 Technologies has launched its STRIDE 2.0 embedded software verification platform, with enhancements to support enterprise-wide deployments.
2006-10-16	Open-source tools ease C++ verification Two engineers published a book on IC verification with C++ and launched a website with free open-source tools that can help IC verification teams.
2006-10-10	VSIA forms verification IP quality workgroup VSIA has formed a quality workgroup to create a verification IP quality worksheet that will address the challenges facing designers as they evaluate and implement standard verification IP components.
2006-9-18	Averant dives deep into formal verification Averant took advantage of Design Automation Conference to roll out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification.
2006-9-15	Synopsis announces verification IP for OCP interface Synopsys said it developed verification IP for the OCP interface in response to customer demand for using its DesignWare Library and VCS Verification Library to verify systems and cores that utilize OCP.
2006-9-6	Website offers free open source C++ IC verification tools Two engineers have launched a website with open-source tools that can help IC verification teams with C++ verification.
2006-9-1	EDA startup offers free verification planning tool Verification-focused EDA startup Jasper Design Automation is making available a free tool for tracking the progress of verification plans.
2006-8-23	GiQuila adopts Mentor's hardware verification system GiQuila has adopted Mentor Graphics' VStation hardware verification system to verify its family of graphics and multimedia ICs for handheld devices.
2006-8-18	Realtek, Cadence collaborate on formal verification design Cadence Design and Realtek Semiconductor announced that they have collaborated to successfully reduce the risk of functional errors on its pilot multi-supply voltage design.
2006-8-11	Cadence introduces line of reusable verification IP Cadence Design Systems recently introduced the Universal Verification Components (UVCs), a new line of reusable verification IP (VIP).

2006-7-26	Formal verification tool promises finer control Averant released the next generation of its formal verification tool, offering what the company claims is the industry's first formal tool to give designers fine control over the tool's thoroughness.
2006-6-15	Cadence offers 'first' transaction-based system verification Cadence unveils 'first' automated end-to-end transaction-based system verification and management solution.
2006-6-1	Breaking the verification barrier Startup OneSpin Solutions believes it has technology that will usher in a new era of IC formal verification. But if this company is successful, the real breakthrough may be one of bringing internal technology from a large integrated device manufacturer into a global, commercial EDA market.
2006-5-24	Verification IP tailored for consumer electronics storage Denali Software announced the availability of a new verification IP package to address the wide range of storage device standards used in consumer electronics products.
2006-4-18	Aldec solution increases network-based design verification Aldec's new mixed-language solution promises to dramatically increase network-based design verification.
2006-4-3	Chips bring fingerprint verification a step further A new fingerprint identification chip takes ID verification technology to the next level.
2006-4-3	PCI Express verification underscores need to plan Complex verification projects have compelled engineers to do more planning to avoid getting lost in the 1,300+ item compliance checklist.
2006-3-6	Cadence, CEVA collaborate to deliver verification process automation Cadence Design Systems, Inc. announced that it will collaborate with CEVA Inc. to deliver a more comprehensive verification process solution for CEVA end customers.
2006-3-3	Firms partner on PCIe verification PLDApplications and EVE have forged a partnership whereby PLDA's x4 PCIe Xpress IP will be embedded in EVE's ZeBu hardware-assisted verification platform.
2006-2-23	Tool generates verification plans from design specs Severity One is starting to sell Relay, a tool that produces reusable, coverage-driven verification plans from textual specifications or user input through a graphical user interface.
2006-1-2	How to improve verification planning 'Good' verification involves a formulaic model to drive the whole verification project with an executable plan.
2005-12-16	IP reuse requires a verification strategy The process of determining the verification strategy for a design IP involves important steps explained here.
2005-12-16	Wrestling functional verification Experts have differing views on how the design process can be improved so as to diminish the need for verification.
2005-12-6	Forte, Summit team up on design and verification flow Forte Design Systems and Summit Design announced their collaboration to deliver an integrated solution that combines the strengths of the Vista SystemC IDE and Cynthesizer SystemC synthesis products.
2005-10-27	Survey finds verification tool use largely unchanged from 2004 The 2005

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