Advancing to true HW/SW co-verification
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2001-11-16 |
| This technical article discusses how advancing to true HW/SW co-verification can enhance embedded systems designs as manufacturers go into deeper submicron processes |
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| Perform integrated HW/SW verification
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2008-01-02 |
| As the lines marking the responsibilities of HW/SW teams and who is responsible for implementation and debug are getting blurred, new methodologies must be adopted to effectively validate an entire IP or silicon solution. The ability to efficiently and optimally design, and perform system-level verification can result in a significant competitive advantage, especially as software solutions become expected deliverables along with complex IP or silicon |
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| Accelerate processor verification through testbench infrastructure reuse
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2011-09-01 |
| Find out how specialised processor verification IP can eliminate historical development and maintenance commitments |
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| Reconfigurable computing accelerates network device verification
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2001-02-01 |
| This technical paper describes the use of reconfigurable computing (RCC) coprocessor technology and its attendant software to speed the verification of a large networking device |
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| Formal verification by equivalence checking in deep sub-micron designs
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2000-09-01 |
| Equivalence verification tools compare the logical behavior of two circuits while ensuring a consistent design flow. They aim to combine structural checking with handling of multi-million gate designs in a small memory footprint |
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| Quality verification and validation
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2002-06-01 |
| Know the fundamental theory and techniques of verification and validation, and see how they have been successfully applied in the creation of high quality embedded software |
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| Address verification issues with scalable methods
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2007-04-02 |
| This article examines how scalable verification, design for verification, and strategies that include abstraction, assertion-based techniques, and improved debugging methods address the fundamental challenges facing design teams |
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| Co-verification speeded up for design
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2001-06-16 |
| Innoveda's boosted V-CPU hardware/software co-verification system through a link with Axis Systems' simulation accelerator can increase the performance of hardware portions of the co-verification process |
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| An integrated approach to PCI verification in SoCs
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2001-11-01 |
| This article looks at the device verification strategy and implementation of a typical PCI subsystem design in order to improve SoC designs |
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| Formal verification for IP soft core
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2003-11-17 |
| Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them |
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| Transaction-based method supports co-verification
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2004-04-01 |
| This paper describes how engineers doing SoC verification can be more efficient by using a single, reconfigurable verification system, applications and a unified methodology |
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| What is formal verification
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2010-05-21 |
| Functional verification is a critical element in the development of today's complex digital designs. Hardware complexity growth continues to follow Moore's Law, but verification complexity is even more challenging |
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| Formal verification of an MPEG decoder chip
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2001-06-01 |
| This article outlines the application of formal verification through model checking of the control unit in a DVD decoder chip |
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| Tackling physical verification below 90nm
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2005-05-02 |
| The article reviews the key challenges of physical verification below 90nm and the methodologies needed to tackle them |
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| Mixed-signal simulation in design, verification
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2005-07-01 |
| Find out how the Virtuoso AMS Designer solution simulates mixed-signal chips throughout design and verification |
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| Verification reuse ensures predictable design
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2002-07-16 |
| Find out ways to make verification efforts reusable using the National Semiconductor Geode GX2 system so that integration stages become predictable instead of schedule black holes |
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| Hardware/Software co-development and SoC verification
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1999-09-01 |
| Different tools and methods are needed to address system-level architecture, hardware/software co-development, and full verification of SoCs in their target environments. Rather than inventing new solutions, leverage techniques proven in the PCB systems world |
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| How to improve verification planning
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2006-01-02 |
| ...Good' verification involves a formulaic model to drive the whole verification project with an executable plan |
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| Solving problems early on using co-verification
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2004-11-16 |
| Learn the importance and benefits of hardware and software co-verification before the physical design becomes available |
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| Co-verification of an RTOS in a SoC
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2002-01-16 |
| This technical article discusses the evolution of co-verification in HW/SW development as it has evolved from an optional requirement to a mandatory one in SoC designs |
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| Solving today's problem of SoC verification
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2010-01-22 |
| As more complex, mixed-signal SoC designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed-signal verification presents a unique challenge as the analog portion of the design requires highly accurate and time-consuming, analog simulation |
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| SystemVerilog enhances assertion-based verification
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2005-06-16 |
| ABV leverages designer knowledge and automatic verification methods to stress-test the design before tape-out. Find out how |
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| Closing the 'quality gap' in functional verification
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2009-12-08 |
| This article discusses the application of mutation-based testing techniques to measure and drive improvement in all aspects of functional verification quality for simulation-based environments as a solution to these problems |
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| Dealing with formal verification constraints
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2010-02-19 |
| Formal model checkers are indispensable, complementing simulation for block-level verification in an ever-challenging design environment. Constraints make a formal tool tick |
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| Verification tool speeds complex IC out the door weeks ahead of schedule
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2002-02-01 |
| This technical article discusses speeding up design and verification of complex ICs without sacrificing quality to beat competition |
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| Perform assertion-based verification in mixed-signal design
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2011-11-03 |
| Understand how assertion-based verification can address the challenges in analog/mixed-signal verification |
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| Full-chip verification for building nanometer memories
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2002-05-01 |
| Verification tools can greatly facilitate memory design, where designers face a combination of evolving circuit complexity and increasing size in dealing with massive memory arrays |
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| Chips bring fingerprint verification a step further
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2006-04-03 |
| A new fingerprint identification chip takes ID verification technology to the next level |
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| Eliminating the problems of dual physical verification
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2003-05-02 |
| A single verification tool that can perform fast interactive verification on cells and blocks, as well as fast and accurate batch verification on full-chip SoCs, is essential to meet today's time-to-market schedules |
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| Automate formal verification for OCP
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2008-09-01 |
| The automation of formal protocol verification using VIPs enables a rapid and exhaustive verification of critical IP interfaces. Once a VIP library is written and tested, it can be re-used to improve the verification quality and shorten the verification schedule. VIPs can also be used to ease the verification of high-level system properties since they provide a "free" environment |
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