Implement message-driven testbench for FPGAs
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2004-12-16 |
| Crack the code in improving test implementations--a message driven testbench may just do the trick |
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| Accelerate processor verification through testbench infrastructure reuse
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2011-09-01 |
| Find out how specialised processor verification IP can eliminate historical development and maintenance commitments. |
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| Configuring the testbench using OVM configuration classes
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2010-03-31 |
| This technical paper is a testimony to the fact that configuration classes, when used properly, greatly improve the configurability and adaptability of a verification environment. |
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| Grasp SystemVerilog testbench debug and analysis
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2008-10-16 |
| Verifying SoC designs is becoming more complex. Fortunately, SystemVerilog addresses the complexity challenge, and enables advanced verification methodologies and automation. |
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| Employ advanced logging techniques for SystemVerilog
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2009-04-30 |
| Logging has been widely used in systems and software environments. And most SystemVerilog libraries being used today provide some built-in utilities for logging information from the testbench to low-level text files that can be analyzed after simulation |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support |
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| Keeping up with complex intellectual property
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2007-10-16 |
| The verification of IP cores continues to become more complex and time-consuming, especially for processor cores such as CPUs, floating-point units and DSPs. The challenge is to design and verify a new embedded vector processor with significant enhancements over its predecessor. |
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| Debugging stimulus generation in VMM, OVM testbenches
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2009-05-22 |
| This article reviews the components of stimulus generation in the VMM and OVM environments, and outlines a typical layered stimulus solution. It also takes a look at the different capabilities available for debugging |
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| Flow is shaky for programmable SoCs
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2001-03-01 |
| Programmable SoC designs are becoming the trend of the future thanks to the greater density of today's programmable devices and the availability of efficient microprocessors. Unfortunately the CAD flows for these devices are far from being robust. |
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| Questions for SystemC
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2001-05-16 |
| OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement. |
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| What is formal verification?
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2010-05-21 |
| Functional verification is a critical element in the development of today's complex digital designs. Hardware complexity growth continues to follow Moore's Law, but verification complexity is even more challenging. |
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| A practical way of inspecting IP quality
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2011-10-12 |
| Find out how to set up a process which can give you solid incoming IP quality inspection—a process that quite likely finds potential problems you may not have checked before, all with a minimum of overhead both in maintenance and in cycle time. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| Oki, Lexra roll out prototyping boards for SoCs
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2001-04-15 |
| This article discusses Oki Semiconductor and Lexra Inc.'s board products intended to speed time-to-silicon for complex SoC designs. |
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| Closing the 'quality gap' in functional verification
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2009-12-08 |
| This article discusses the application of mutation-based testing techniques to measure and drive improvement in all aspects of functional verification quality for simulation-based environments as a solution to these problems. |
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| Perform assertion-based verification in mixed-signal design
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2011-11-03 |
| Understand how assertion-based verification can address the challenges in analog/mixed-signal verification. |
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| Equivalency checking for sequential changes
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2006-05-16 |
| The ability to make and verify sequential changes improves designers' productivity, enabling them to meet strict power, timing and area goals. |
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| Mixed-signal simulation in design, verification
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2005-07-01 |
| Find out how the Virtuoso AMS Designer solution simulates mixed-signal chips throughout design and verification |
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| Verification reuse ensures predictable design
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2002-07-16 |
| Find out ways to make verification efforts reusable using the National Semiconductor Geode GX2 system so that integration stages become predictable instead of schedule black holes. |
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| Hardware/Software co-development and SoC verification
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1999-09-01 |
| Different tools and methods are needed to address system-level architecture, hardware/software co-development, and full verification of SoCs in their target environments. Rather than inventing new solutions, leverage techniques proven in the PCB systems world. |
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| Recycle RTL testbenches to verify IP models
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2003-09-01 |
| Future work in the area of reusing RTL testbenches to verify TLM blocks will focus on fully automating the process, including automatic fault checking. |
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| Deterministic simulation of an ARM core
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2001-12-01 |
| This technical article discusses the deterministic and random testing techniques used to verify complex cores such as the ARM946E-S architecture. |
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| Testing modems, xDSL and ISDN in a shared environment
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2003-12-16 |
| Dial-up modems, ISDN terminal adaptors and xDSL modems will be more commonly used in a shared environment with the increase in computing power. |
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