Tips for compiling software to gates
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2005-07-01 |
| VHDL and Verilog are past their prime and will soon be replaced by other C-like design languages |
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| Assertion methodologies for Verilog design
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2002-01-16 |
| This article describes the different approaches designers need to undertake in dealing with assertion methodologies for hardware designs expressed in Verilog or VHDL |
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| DSP tips for designing a DECT/GSM fractional-N frequency synthesizer
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1999-09-09 |
| This paper describes how to implement a fast and flexible frequency divider in a fractional N frequency synthesizer in a dual-mode transmitter for DECT/GSM with a high component reuse. The divider is described in VHDL and simulated for one of the two standards |
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| High-performance delta-sigma ADCs ease converters' limitations
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2006-08-16 |
| The integration of ADCs and CPUs has forced IC manufacturers to replace transistor-level design with VHDL code, synthesis and standard-cell libraries. This has resulted in lower-performance analog circuitry |
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| Long road ahead for analog synthesis
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2000-05-01 |
| It may be a bit like asking why can't women be more like men, but the question, "Why can't analog be more like digital?" is the most common complaint among engineers attempting to use analog design tools. Synthesis (the automatic generation of physical circuitry from a high-level language description) is one area where analog design departs drastically from digital. |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
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| Programmable system chips move forward
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2001-05-01 |
| Using dedicated hardware to boost real-time performance of embedded systems is a common practice and, with the introduction of PSCs, software engineers will learn how to boost performance of timing-critical software functions. |
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| Peripheral model makes dual run
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2001-03-01 |
| With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process. |
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| A faster way to run Reed Solomon decoders
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2001-01-01 |
| This technology news describes the new Reed-Solomon (RS) decoder architecture that can process multiple symbols per clock cycle. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| Programmable-chip methods get fresh look
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2001-05-01 |
| At the current lithographic resolutions, PLDs offer the potential of producing "systems on programmable circuits." |
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| How FPGAs boost medical imaging
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2011-11-29 |
| Learn how field-programmable gate arrays and other computing elements can enhance imaging techniques such as optical coherence tomography. |
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| How to reset an FPGA
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2011-08-22 |
| Know the various reset options available for FPGAs, as well as their advantages and disadvantages. |
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| Accelerate processor verification through testbench infrastructure reuse
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2011-09-01 |
| Find out how specialised processor verification IP can eliminate historical development and maintenance commitments. |
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| Syntax raises RTL abstraction level
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2001-05-16 |
| A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages. |
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| Mentor CEO argues FPGAs will drive platforms
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2001-05-01 |
| This article describes how FPGA platforms will innovate designs and how engineers can make the most out of it. |
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| Questions for SystemC
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2001-05-16 |
| OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement. |
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| Understand, test OCP SystemC channel models
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2008-06-02 |
| The OCP Protocol is a high-performance and bus-independent interface protocol between intellectual property cores that provides a standard for Electronic System Level design. It improves IP core reusability, making more predictable and productive SoC designs. |
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| Overcome challenges of ASIC/SoC prototyping with FPGAs
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2011-10-24 |
| Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy. |
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| Accelerate embedded system design with NI's LabVIEW platform
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2006-09-14 |
| As the pressure to get products to market faster continues to increase, embedded systems are growing more sophisticated and complex. |
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| Why compliance to PoE safety standards is crucial when moving beyond 60W
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2012-01-31 |
| Read about the realities of delivering high-power levels safely and effectively under the latest PoE standard. |
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| Open source hardware
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2002-12-02 |
| This technical article discusses how open-source techniques in hardware design are still impossible to achieve with the current technology available to engineers. |
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| Logic suppliers seek ways to embed FPGAs
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2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
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| Perform assertion-based verification in mixed-signal design
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2011-11-03 |
| Understand how assertion-based verification can address the challenges in analog/mixed-signal verification. |
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| Speeding up medical imaging process using FPGA
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2011-09-01 |
| Read about the use of FPGA platform and a synthesis tool called Impulse C to speed up a statistical line of reaction estimation for a high-resolution PET scanner. |
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| Lower costs through design tool performance
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2005-03-16 |
| The ISE software has capabilities that reduce design and verification times, attaining design closure faster |
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| Using parallel-distributed HDL simulation
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1999-10-01 |
| Parallel-distributed simulations can reduce the time required to perform HDL simulations without dramatically affecting existing design flows. While the theoretical limit of parallel simulations is not reached, the simulation times do approach the limit within reason. |
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| Co-design method enables speech recognition SoC
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2002-09-16 |
| Two STMicroelectronics design engineers use a system-level design flow based on the CoWare N2C method to create a speech-recognition capable SoC. |
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| Synthesize SoCs using C-based design flow
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2001-08-01 |
| This is a case study in which an SoC was synthesized for Columns Ltd using a C-based design flow. |
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| The advantage of using logic BIST for ASIC designs
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2000-12-01 |
| This technical paper reveals the advantage of using logic BIST for ASIC designs. |
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