DFT and BIST for SoC designs
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2000-09-01 |
| Design for testability (DFT) and built-in self-test (BIST) techniques are widely publicized in SoC (Systems-on-Chip) designs, but are still often only thought of as "back end" concerns. In reality, the importance of these techniques insures the highest fault coverage and shortest production test time in the device design cycle |
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| DSC is an SoC innovation
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2005-07-01 |
| A digital signal oscillator is an SoC architecture that combines the control features of a 16bit MCU with the DSP's extensive functionality |
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| The case for real-time visibility in SoC designs
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2006-04-17 |
| Visibility into an SoC requires a mix of hardware and software mechanisms to collect data within the chip itself |
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| Vendors must support IP reuse in SoC
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2003-04-16 |
| The need for IP reuse will increase as design complexity grows to higher levels. This support structure forms an invisible layer that would make SoC/IP-ASIC engagements as seamless as possible |
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| Co-design method enables speech recognition SoC
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2002-09-16 |
| Two STMicroelectronics design engineers use a system-level design flow based on the CoWare N2C method to create a speech-recognition capable SoC |
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| Convergence through scaleable SoC solutions
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2001-08-09 |
| This conference technical paper describes the functions of a SoC-based VoP processor and its many benefits over solutions based on reduced customer costs and improved performance |
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| Programmable logic enables powerful SoC solutions
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2002-10-01 |
| With the ability to embed complete systems on a single FPGA, programmable logic has enabled a new realm of powerful yet very flexible SoC solutions |
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| Platform-based SoC design comes of age
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2006-04-03 |
| Ongoing silicon scaling has prompted the IC industry to seek new design methodologies, the most notable of which is platform-based SoC design |
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| System verification: Essential for digital wireless system-on-chip (SoC) designs
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1999-09-09 |
| This paper discusses verification and hardware/software co-verification in SoC applications. It also deals with the SoC verification issue, and not the details of designing 3G wireless applications |
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| Programmable SoC For Wireless, Handheld, Data Communication And Industrial System Designs
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2001-03-26 |
| This paper presents some high-speed Programmable SoC (PSoC) devices that include programmable digital and analog function blocks designed for wireless, handheld, datacom and industrial applications |
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| Reconfiguring SoC according to Garp
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2001-05-01 |
| Programmable SoC components, containing a microcontroller and reconfigurable hardware, promise the flexibility of software and the performance of hardware |
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| Embedded test complicates SoC realm
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2001-03-01 |
| SoC devices today implement a variety of specialized microelectronic functions. Those functions, sometimes with embedded systems, typically comprise of hardware or software design objects |
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| Co-verification of an RTOS in a SoC
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2002-01-16 |
| This technical article discusses the evolution of co-verification in HW/SW development as it has evolved from an optional requirement to a mandatory one in SoC designs |
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| Single-mask simplicity needed for SoC
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2001-06-01 |
| The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices |
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| Solving today's problem of SoC verification
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2010-01-22 |
| As more complex, mixed-signal SoC designs continue to stress verification methodologies and schedules, designers need new approaches in solving today's test challenges. Mixed-signal verification presents a unique challenge as the analog portion of the design requires highly accurate and time-consuming, analog simulation |
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| An Appreciation Of SOC On Bluetooth Headset
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2001-07-03 |
| This paper introduces the fundamentals of Bluetooth headset, walks through the process of implementing a headset-specific SoC solution, and presents a usage model of the next-generation Bluetooth headset |
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| An Appreciation Of SOC On Bluetooth Headset
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2001-03-29 |
| This paper introduces the fundamentals of Bluetooth headset, walks through the process of implementing a headset-specific SoC solution, and presents a usage model of the next-generation Bluetooth headset |
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| Lockdown! Random numbers secure network SoC
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2004-02-02 |
| The generation of truly random numbers for cryptographic applications on SoC network is a complex task. To meet the increasing demand for security in applications such as VPNs, designers must embrace that complexity |
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| System specs drive multiprocessor SoC
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2002-02-16 |
| SoC design requires new tools and a different skill set than traditional ASIC chip design. The case study illustrates new challenges and describes methodologies to address them |
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| Passing the SoC test with flying colors
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2002-10-16 |
| The key concern of product developers, SoC design houses and wafer fabs is to provide higher performance and functionalities of SoC at the lowest cost |
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| Beat the SoC challenge with a tuner
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2008-01-02 |
| Custom integrated SoC designs are a great way to replace multiple individual ICs and support circuitry. The benefits are many: you save space, you save power, you save money. However, there is a challenge to overcome |
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| SoC boosts speech-recognition systems
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2006-12-18 |
| The SoC is an optimized solution to embedded applications such as toys, voice based remote control and speech recorder. SoC boosts speech-recognition systems |
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| Overcome challenges of ASIC/SoC prototyping with FPGAs
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2011-10-24 |
| Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy. |
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| SuperHyway provides SoC backbone
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2000-12-01 |
| A step ahead of CompactPCI, Compact Packet Switching Backplane (cPSB) is emerging as a viable solution for interconnect problems. |
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| Network the digital home with SoC architecture
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2007-05-16 |
| Complete SoC solutions will be critical in the development of digital-home applications, as they will provide all of the hooks for integrating with target applications |
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| DBIST answers advanced SoC test challenges
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2003-04-16 |
| Due to the exponential growth in the time and cost to apply scan tests on sophisticated SoCs, Synopsys Inc. releases its DBIST as a key capability in its new product for advanced SoC testing, the DFT Compiler SoCBIST |
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| Employing SoC for cost-effective 3D designs
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2011-10-01 |
| Here's a look at the current 3D active shutter architectures vis-à-vis the next generation solutions now available. |
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| Equivalence checking for SoC blocks
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2001-11-16 |
| This technical article explains that as custom blocks become increasingly important for SoCs, equivalence checking between transistor-level implementation and behavioral modeling become equally significant design factors. |
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| Power distribution for deep-submicron SoC designs
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2001-05-01 |
| Power grid verification is becoming an imperative in deep-submicron design. |
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| Selecting a CPU core for multi-CPU SoC designs
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2003-03-03 |
| This article examines the many features of processor cores being considered for multi-CPU designs. |
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