| Syntax raises RTL abstraction level
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2001-05-16 |
| A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages |
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Recycle RTL testbenches to verify IP models
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2003-09-01 |
| Future work in the area of reusing RTL testbenches to verify TLM blocks will focus on fully automating the process, including automatic fault checking |
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| Conducting at-speed test at RTL (Part 1
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2011-04-11 |
| Learn how to facilitate at-speed test at the register transfer level. |
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| Conducting at-speed test at RTL (Part 2
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2011-04-15 |
| Find out more about at-speed timing closure rules and at-speed coverage. |
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| Test coverage enhancements at the register transfer level
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2001-01-01 |
| This technology article describes the RTL buffer insertion and fault grading that helps identify untested functions and low-fault coverage areas where added test vectors can be generated |
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| The need for an EDA API
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2001-05-01 |
| There are a lot of skepticism with Cadence's IE (Integration Ensemble) tool-with capabilities that include floorplanning, RTL synthesis, placement, routing, extraction and analysis. The arguments for a single tool that encompasses all these features are compelling, but will the tools live up to engineer's expectations |
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| Functional verification of 10M-gate SoCs
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2002-03-01 |
| This technical article discusses the advantages of implementing the "white-box" design methodology for instrumenting RTL structures inside very large SoC designs as compared to the traditional black-box test suites |
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| Cadence's 'all-in-one' tool gets skeptic reviews
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2001-05-01 |
| Cadence's Integration Ensemble (IE) is the first single tool that can take a hierarchical chip design all the way from synthesizable RTL code through a GDSII layout file and designers are raising an eyebrow if it will perform as well as it promises |
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| Choosing the right design flow model with integrated architecture
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2004-02-02 |
| Users of ASIC, COT and COPD models are finding that flows based on an integrated RTL-to-GDSII system can offer additional benefits when fully leveraged |
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| Create multistandard video engines
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2007-05-16 |
| Unlike conventional 32bit processors that suffer from performance bottlenecks, programmable processors provide more flexibility than RTL blocks to support multiple video standards |
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| Build efficient datapath designs
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2005-10-03 |
| This article proposes RTL coding guidelines and a context-sensitive RTL datapath synthesis for improving design productivity |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
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| Programmable system chips move forward
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2001-05-01 |
| Using dedicated hardware to boost real-time performance of embedded systems is a common practice and, with the introduction of PSCs, software engineers will learn how to boost performance of timing-critical software functions. |
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| Extraction method verifies IP functions
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2001-06-01 |
| To keep in pace with silicon technology advancement, verification of the reused custom logic against its original counterpart should be considered as an integral part of the reuse process. |
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| Emulation or prototyping for silicon success?
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2001-04-15 |
| With the high-stakes financial and time-to-market risks involved in designing ICs, which verification method is necessary for first-pass silicon success? |
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| Embedded test complicates SoC realm
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2001-03-01 |
| SoC devices today implement a variety of specialized microelectronic functions. Those functions, sometimes with embedded systems, typically comprise of hardware or software design objects. |
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| Long road ahead for analog synthesis
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2000-05-01 |
| It may be a bit like asking why can't women be more like men, but the question, "Why can't analog be more like digital?" is the most common complaint among engineers attempting to use analog design tools. Synthesis (the automatic generation of physical circuitry from a high-level language description) is one area where analog design departs drastically from digital. |
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| How to reset an FPGA
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2011-08-22 |
| Know the various reset options available for FPGAs, as well as their advantages and disadvantages. |
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| Accelerate processor verification through testbench infrastructure reuse
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2011-09-01 |
| Find out how specialised processor verification IP can eliminate historical development and maintenance commitments. |
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| A high-level synthesis methodology for complex FPGA
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2010-06-25 |
| This article describes the implementation of Virtual Line Crossing Detection (VLCD) on an Altera Stratix II FPGA and the methodology we used. |
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| Flow is shaky for programmable SoCs
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2001-03-01 |
| Programmable SoC designs are becoming the trend of the future thanks to the greater density of today's programmable devices and the availability of efficient microprocessors. Unfortunately the CAD flows for these devices are far from being robust. |
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| Address hardware/software integration issues with combined prototyping solutions
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2012-01-11 |
| Find out how to reap the individual advantages of prototypes in combination with other prototyping techniques. |
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| Optimizing OCP slave memory behavior
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2009-11-12 |
| Verification IP for open-core protocol (OCP) is generally used to achieve one of two main verification objectives—at the module level to test OCP components and their interfaces, or at the bus fabric level when some or all of the components may be replaced by the verification IP to test the behavior of a system. |
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| Optimizing ASIC design flow for SoPCs
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2001-05-01 |
| System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly. |
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| Questions for SystemC
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2001-05-16 |
| OSCI is supposed to be an "open" and independent standards effort, but Synopsys still has total control over the license agreement. |
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| Identifying the 4G PHY architecture design challenges
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2011-12-20 |
| LTE-A is an evolution of the LTE standard with a number of enhancements that create significant design challenges. |
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| Understanding high-level synthesis design's advantages
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2010-04-26 |
| It is vitally important to verify the design before performing high-level synthesis, not after. It is not effective to synthesize a design that does not work. |
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| Optimizing power in SoC designs
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2010-07-28 |
| Current methods employed by designers for optimizing power are inefficient and unproductive, making it difficult to know when a design is fully power optimized. |
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| A practical way of inspecting IP quality
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2011-10-12 |
| Find out how to set up a process which can give you solid incoming IP quality inspection—a process that quite likely finds potential problems you may not have checked before, all with a minimum of overhead both in maintenance and in cycle time. |
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| Overcome challenges of ASIC/SoC prototyping with FPGAs
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2011-10-24 |
| Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy. |
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