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Syntax raises RTL abstraction level
A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages. |
2001-05-16 |
Verification firm starts partners program
Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry |
2001-04-15 |
Switch fabrics pave way to scalable networking
Topics span from Infiniband design hurdles to in-box benefits of RapidIO, along with various on-chip switch schemes like SuperHyway for highly integrated system chips |
2000-12-01 |
Single-mask simplicity needed for SoC
The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices |
2001-06-01 |
Peripheral model makes dual run
With complex embedded-system designs exceeding 1 million gates, verification has become the critical bottleneck in the design process |
2001-03-01 |
Optimizing ASIC design flow for SoPCs
System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly |
2001-05-01 |
ASIC generation revamped for IP reuse
For designers, the linchpin for complete IP reusability is the programmable VLIW processor core, along with programmable buses and interface ports |
2001-06-01 |
Logic suppliers seek ways to embed FPGAs
Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility |
2001-03-01 |
Creating a broadband digital home
A broader perspective of home networking is quickly evolving, one that takes into account the full spectrum of bundled services that can be delivered over a broadband pipe. |
2001-03-01 |
Same-die tactic eases DDR transition
The industry consensus is clear: DDR's time has come. Now what design issues must engineers consider, and what can DRAM suppliers do to make this memory transition happen smoothly and seamlessly |
2001-04-15 |
Oki, Lexra roll out prototyping boards for SoCs
This article discusses Oki Semiconductor and Lexra Inc.'s board products intended to speed time-to-silicon for complex SoC designs. |
2001-04-15 |
Drive your large LCD with PPDS
There is a need for a robust and reliable LCD interface solution to transmit through less data lines working at higher frequency. Point-to-Point Differential Signaling (PPDS) ensures reliable data transmission from the timing controller to the column driver/driver ICs through fewer data lines compared to the traditional multi-drop architecture |
2008-04-01 |
CompactPCI answers next-generation needs
A step ahead of CompactPCI, Compact Packet Switching Backplane (cPSB) is emerging as a viable solution for interconnect problems. |
2000-12-01 |
High PoE made simple
According to National Semiconductor's Grant Smith, high Power-over-Ethernet (HPoE) standards are still to be resolved. What is expected by most is that the voltage source will be increased to 53Vdc, usable current from each line to about 750mA, and the total resistance in the cable be limited below 12.5Ω. But for some applications, this is not enough power. One solution is to use multiple Ethernet lines, but this raises the problem of power sharing. |
2008-03-03 |
1394: Still the best bus for network backbones
If imitation is the highest form of flattery, those who advocate the 1394 multimedia standard ought to feel proud. Every time a group or company touts a new specification, it claims the new spec will do what 1394 already does. |
2001-05-16 |
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