Ultrafine-line lithography for next-gen apps
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2000-11-01 |
| This technical article describes the ultrafine-line technology applied by researchers at the Georgia Institute of Technology for next-generation silicon device technology. |
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| Scatterometry-based critical dimension and profile metrology
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2002-09-16 |
| This technical article discuss how as geometries are pushed below 0.15m, critical dimensions and feature profile metrology has become key to overall control of lithography |
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| A review of 10GBase-T technology
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2011-10-21 |
| Here's a discussion on the basic operations of a 10GBase-T transceiver and the inherent advantages of 10GBase-T technology as compared to alternatives, such as optical fiber and coaxial copper. |
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| Avoid design snags with silicon contour predictor
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2007-09-17 |
| Designers can improve parametric yield and chip performance by accurately determining the impact of systematic variations during design. |
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| Library generators employ optical correction at cell level
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2001-03-01 |
| This technology article discusses the enhancement of cell-based designs with the evolution of EDA. |
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| Optimizing DSPs for wireless world
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2001-04-15 |
| Complexities in next-generation requirements is taxing the capabilities of traditional DSP technology and design methodologies, causing a need for industry business models to be drastically redefined. |
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| Single-mask simplicity needed for SoC
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2001-06-01 |
| The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices. |
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| Evolution of manufacturing closure for advanced nodes (Part 1)
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2010-09-20 |
| Manufacturing closure has become a key design challenge at smaller technology nodes such as 32nm and 22nm. This article, the first of three parts, discusses the new challenges in manufacturing closure. |
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| Broadband illumination captures critical defects
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2007-09-17 |
| This article demonstrates that a tunable broadband brightfield approach has several advantages over a single-wavelength approach for meeting new inspection challenges and generating higher capture rates of yield-impacting defects. |
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| Tackling physical verification below 90nm
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2005-05-02 |
| The article reviews the key challenges of physical verification below 90nm and the methodologies needed to tackle them |
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| Stir manufacturing into design effectively
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2007-03-16 |
| Semiconductor companies looking to maximize yield will need to deploy more effective methods to account for manufacturing effects early in IC development. |
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| Solder paste process control for CSPs and 0201s
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2003-01-16 |
| This technical article discusses a more effective strategy to improve first pass yields and prevent defects from occurring in CSPs and 0201s. |
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| Beyond pass/fail: Exploring device failures
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2005-03-16 |
| DFT will soon be used for reliable device-failure analysis and become the keystone of rapid yield improvement |
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| Team up to win the yield game in the nm era
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2008-03-03 |
| Designers and manufacturers are two sides of the same team, sharing a common goal—yield. To win out, they need to align their strategies, their skills and their knowledge, and work together to overcome the challenges. That's the way the game is played in the nanometer era, says Anthony Nicoli of Mentor Graphics. |
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