Scale JTAG to meet evolving embedded needs
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2006-06-16 |
| The biggest hurdle to JTAG adoption and integration is recognizing that a strategy is needed across multiple development disciplines. Once this step has been initiated and initial adoption of ATPG support and a JTAG mux device is completed, it becomes easier to evaluate or implement additional new JTAG capabilities one small step or generation at a time |
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| Beating the BGA test blues
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2006-03-01 |
| Boundary scan via JTAG can be used in a nontraditional way to determine whether a signal is connected properly to the BGA |
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| Testing SoC interconnects using boundary scan
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2004-08-02 |
| Delay violations occurring in the interconnects of high-speed SoCs can be tested using JTAG boundary scan architecture |
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| Evaluation kit boosts MCU-based system designs
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2006-07-01 |
| This article describes a range of evaluation kits that considerably ease this changeover, offering advanced features such as USB powering of the board, JTAG debugging and single-button Flash download |
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| Advances in 3D-IC testing
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2012-02-03 |
| Read about the design-for-3D-test architecture and implementation flow developed by researchers at Industrial Technology Research Institute based on the Synopsys test solution. |
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| Dolphin, Raisonance team-up on microcontroller core
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2001-06-01 |
| The Dolphin Integration and Raisonance team up to create a hierarchical development system for the 8051 8-bit microcontroller core is expected to bring enhancements in the field of control technology. |
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| Overcome challenges of ASIC/SoC prototyping with FPGAs
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2011-10-24 |
| Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy. |
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| Reduce yield fallout by avoiding over and under at-speed testing
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2011-10-14 |
| Here's a look at the problems associated with SoC at-speed testing such as overtesting and under-testing. This article also provides suggestions on how to overcome them. |
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| Logic suppliers seek ways to embed FPGAs
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2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
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| Startup preps 5Gbps backplane transceiver
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2001-06-16 |
| In a bid to build a better bit pipe on the backplane, Accelerant Networks is preparing to roll out a proprietary CMOS transceiver that harnesses multilevel signaling technology. |
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| Test industry catches up with engineering demands
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2000-01-01 |
| The test industry has been catching up with the demand for technical features during 1999. The year ahead is expected to be slated for both an increased demand from engineers and better test solutions from vendors. |
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| The advantage of using logic BIST for ASIC designs
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2000-12-01 |
| This technical paper reveals the advantage of using logic BIST for ASIC designs. |
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| COT design flow validates SoCs
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2002-05-01 |
| This technical article details the approach two chip companies used to validate a COT (customer-owned tool) flow from beginning to end resulting in a complete working silicon. |
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| FPGA on-chip debug with off-chip benefits
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2003-02-17 |
| This article will address some of the limitations of on-chip debug and show users an alternative that combines the best of both worlds--on-chip debug with off-chip, deep sample storage. |
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| Perform trouble-free test of BGAs, interconnects
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2006-11-16 |
| One of the most confounding tasks a hardware engineer comes upon happens when the first spin of a PCB arrives on the desk. With no way to probe under a ball BGA chip, engineers need tips in performing easy test of board, BGAs and interconnects. |
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