Vendors must support IP reuse in SoC
|
2003-04-16 |
| The need for IP reuse will increase as design complexity grows to higher levels. This support structure forms an invisible layer that would make SoC/IP-ASIC engagements as seamless as possible |
|
| ASIC generation revamped for IP reuse
|
2001-06-01 |
| For designers, the linchpin for complete IP reusability is the programmable VLIW processor core, along with programmable buses and interface ports |
|
| QIP metric streamlines the process
|
2006-02-16 |
| The process of evaluating and integrating IP to maximize benefits of reuse is as important as the decision to reuse |
|
| Slashing design time with the IP evaluation model
|
1999-10-01 |
| A new paradigm in design reuse eases your job of picking the right IP for your application, and lets you focus on more pressing issues in the design process. It calls for just downloading the IP, parametrizing it and evaluating it before licensing the core |
|
| Fitting last year's IP to today's processes
|
2001-06-01 |
| Changing design styles in IP reuse should prompt engineers to be more receptive to future design shifts in the industry |
|
| Step up handset test with adaptive test case
|
2007-11-01 |
| Developers can significantly simplify handset testing by zeroing on the development of reusable test logic that can be used with automated testing platforms. An adaptive test case methodology boosts test case development and enables reuse of test IP across test cases, handset platforms and OS |
|
| Analog, mixed-signal design flow found wanting
|
2001-06-16 |
| Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper. |
|
| Address hardware/software integration issues with combined prototyping solutions
|
2012-01-11 |
| Find out how to reap the individual advantages of prototypes in combination with other prototyping techniques. |
|
| Silicon prototyping verifies IP functions
|
2001-06-01 |
| SoC designers are confronting several important tasks in optimizing next-generation products. New systematic approaches are needed to ensure that IP can be transferred from one process geometry to the next |
|
| Logic suppliers seek ways to embed FPGAs
|
2001-03-01 |
| Driven by the convergence of communications, computing and consumer applications, SoC design complexity increases the time required to bring competitive products to market, putting a premium on design speed and flexibility. |
|
| Leveraging PLDs for embedded system functionality
|
1999-03-01 |
| You can directly apply the techniques and tools used in Internet Reconfigurable Logic (IRL)-based enterprise development to embedded systems and thus enhance their capabilities. |
|
| Packet rings aim at metro nets
|
2001-05-01 |
| Resilient packet ring (RPR) is a new technology that optimizes unique requirements of metro networks by defining a MAC with two network interfaces. |
|
| Carry out cache coherence in a MIPS32 multicore design
|
2008-11-03 |
| Here's an example of how the Open Core Protocol was used to reconfigure the basic MIPS32 architecture to support cache-coherent traffic within an embedded multicore cluster. |
|
| SoCs likely to pose heading-off test problems
|
2000-12-01 |
| This technology news article describes the problems and solutions test engineers should face when confronting SoC designs. |
|
| Researchers team up for Java-based IP query tool
|
2001-05-16 |
| A collaborative effort is producing a new Java-based tool that promises to allow users to easily query IP repositories and commercial databases via the Web |
|
| Accelerate processor verification through testbench infrastructure reuse
|
2011-09-01 |
| Find out how specialised processor verification IP can eliminate historical development and maintenance commitments |
|
| SuperHyway provides SoC backbone
|
2000-12-01 |
| A step ahead of CompactPCI, Compact Packet Switching Backplane (cPSB) is emerging as a viable solution for interconnect problems. |
|
| EDA Consortium tackles FPGA productivity
|
2001-06-16 |
| The recent EDA Consortium tackled important issues that focus on direct HDL entry and better productivity measurements for designers and engineers. |
|
| Real system-level design challenge: Hardware-firmware integration
|
2001-06-16 |
| For today's engineering co-design, the real system challenge is the hardware/firmware integration. |
|
| Single-mask simplicity needed for SoC
|
2001-06-01 |
| The move to multimillion-gate chips made it necessary to adopt design-reuse strategies for new SoC devices |
|
| Speeding up medical imaging process using FPGA
|
2011-09-01 |
| Read about the use of FPGA platform and a synthesis tool called Impulse C to speed up a statistical line of reaction estimation for a high-resolution PET scanner. |
|
| Plotting the future of mobile digital video recorder
|
2006-01-16 |
| Portable media players need sufficient headroom to accommodate different codecs in the growing multimedia content market. |
|
| Meeting the challenges of co-design
|
2000-03-01 |
| Even though the promise of co-design has not yet materialized, there is a decided benefit in easily transitioning among plausible architectures in order to perform high-level trade-off analysis. |
|
| Platform ASICs deliver reduced cost for many applications
|
2004-07-16 |
| To save time and cost, platform ASICs come with predefined and prediffused layers to which customers can add differentiations. |
|
| System integration technologies support SoC design
|
2001-05-08 |
| System integration is a critical bottleneck in the development of system-on-a-chip technologies. |
|
| Requirements for next-generation PLD tools
|
1999-03-01 |
| This paper describes ways on how to design a multi-million gate PLD using next-generation tools. |
|
| Designing embedded memories using 4G compilers
|
1999-01-01 |
| Embedded memories gain over standalone memories in terms of power consumption, performance, flexibility of use, and test and diagnostics. Use fourth generation compilers to embed memories on a chip to realize the quality and reliability of standalone ones. |
|
| The advantages of using PCB design reuse
|
2000-12-01 |
| This technical article focuses on the benefits of PCB design reuse and discusses the elements that leverage the reuse methodology |
|
| Improving productivity with FPGA design reuse
|
2000-12-01 |
| This technical article describes the most effective way to fill the productivity gap in silicon integration. |
|
| Reusable Intellectual Property for embedded systems software development
|
2000-08-01 |
| One of the most neglected areas of embedded systems software development has been the area of reuse of device drivers and Board Support Packages (BSP). But with a new tool called the Device Driver Development Environment (3DE), you can now accelerate support for the development of BSPs and device drivers |
|
|
|
|
|
|Electronic Components|Computer Products|Trade Show Center
|Site Feedback|Site Map|Help|About Us|Contact Us|Terms of Use|Privacy Policy|Security Commitment