Choosing digital I/O for your output sensor
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2004-05-17 |
| Classify digital output sensors based and point out the critical parameters that should be taken into account when selecting a digital I/O module for your application |
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| Grasp the ins and outs of high-speed I/O
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2004-06-01 |
| While serial I/O would seem to solve the interconnect dilemma facing high-speed designs, parallel interfaces still have their place |
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| Optimize I/O expansion in workstations
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2007-12-17 |
| PCIe switches and PCI-to-PCIe bridges can help get beyond many of the workstation I/O limitations. Steve Moore of PLX Technology invites us to explore how these devices can be used to optimize I/O expansion in high-performance workstations |
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| Creating a third generation I/O interconnect
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2004-09-01 |
| This paper looks at the success of the widely adopted PCI bus, and describes a higher performance next-generation I/O interconnect |
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| Enhancing computer-based I/O for test systems
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2001-09-16 |
| This technical article describes a change in the test and measurement arena as computer-based I/O systems makes their debut |
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| Testing dimensional limits of high I/O flip-chip design
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2001-02-01 |
| The study characterizes underfill materials, examining some large package geometries and design manufacturing processes to avoid defects for I/O counts |
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| A fresh approach to Serdes I/O modeling
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2007-12-17 |
| This paper will discuss need for algorithmic models, the interoperability problem, the need for IBIS BIRD 104 and the benefits systems companies and Serdes IP companies will derive from this new approach. |
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| I/O error monitoring in industrial machine control
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2006-03-01 |
| Find out how you can simplify the monitoring and handling of errors in machine-control units to minimize service costs. |
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| Interfacing for high-speed I/O board designs
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2000-06-01 |
| The most difficult problem for designers of high-performance real-time DSP and data acquisition systems is simply moving data. Many factors contribute to this data-flow dilemma, and traditional methods of handling these tasks are no longer viable. |
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| EMC Basics #5: I/O as crucial circuits
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2011-06-06 |
| Here's a discussion on input/output circuits during EMI circuit board reviews. |
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| FPGA I/O features help lower overall PCB costs
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2004-09-16 |
| Manage board complexity by exploiting advanced features of modern FPGA architectures. |
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| A high-speed serial I/O connector system
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1999-06-29 |
| The rapid deployment and acceptance of Fast Ethernet virtually requires the existence of the Gigabit Ethernet, simply because the backbone must have more capacity and performance than its endpoints. The MetaGig interconnection system is the enabling technology which allows the Gigabit ethernet to be implemented in a cost-effective way over the short haul. |
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| Innovative Digital I/O Signal Switching Technology
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2001-07-02 |
| This paper describes the JAZiO digital signal switching technique for low-latency, high-bandwidth applications, such as DRAMs, SRAMs, CPUs, ASICs, SoCs, etc. |
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| Optimizing I/O protection for ADSL modems
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2003-05-16 |
| By utilizing ordinary phone lines, ADSL tools need protection from electrical risks such as lightning stresses and other power hazards. |
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| Pinout complex FPGAs step-by-step
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2008-12-16 |
| I/OI pin assignment is a challenge when integrating large FPGA devices into PCBs. But with smart I/O planning and new tools, you can remove the pain from the pinout process |
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| Optimize system performance with PCIe
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2008-05-16 |
| PCIe 2.0 is optimizing system performance in many ways. However, long read response latencies that reduce aggregate I/O performance can occur in host-centric PCIe systems when even a single endpoint reads ahead very aggressively to ensure it is never "starved" for data. PCIe Gen 2 switches feature Read Pacing to prevent this kind of performance degradation |
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| Infiniband requires design trade-offs
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2000-12-01 |
| Primary players in the computer industry are developing the Infiniband architecture as the next generation of server I/O, with the intent of eventually replacing PCI |
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| The challenges and potential of GPIB
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2007-10-16 |
| GPIB continues to serve as a reliable I/O interface for a vast number of instruments that are still in use. GPIB also provides a convenient way to manage complex hardware handshaking |
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| Using FPGAs for high-speed serial interface design
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2003-03-17 |
| FPGA provides the bandwidth and flexibility for industry leading high-speed interfaces. Its True-LVDS technology was designed to support the strict timing requirement of up to four high-speed differential I/O protocols |
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| I/Os for distributed automation control
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2005-03-16 |
| This article describes the idea of the industrial CAN I/O module and the data exchange between connected modules being done using a CAN bus |
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| Cadence, Agere tool would foster IC co-design
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2001-05-01 |
| This article describes the Cadence and Agere team-up to develop a tool with chip I/O planning capabilities |
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| The C programmer's guide to Verilog
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2004-06-16 |
| This will look at how to implement PWM in software and then turn the design into a logic block that can run from an FPGA and be controlled via software using a memory-mapped I/O interface |
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| Wireless chip-to-chip link shows promise
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2004-11-16 |
| Proximity Communication is an implementation of such a scalable I/O technology that uses the lithographic pitch of on-chip wires |
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| Ringed bus technology puts twist on switching networks
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2000-12-01 |
| Switch fabric is a fast, concurrent and transparent mechanism for transferring data from multiple sources to multiple destinations within a network via high-speed point-to-point links. |
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| Build distributed test system with LXI oscilloscope
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2008-08-18 |
| The purpose of creating LXI alliance is to simply integrate test systems; improve the throughputs of the test systems; reduce the cost; utilize the mature technologies like Ethernet and 1588; and assure the compatibility among different providers. |
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| Beat serial backplane interface design hurdles
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2007-09-17 |
| Evolution of backplane system requirements in terms of rates and protocols is inevitable and engineers will face interface design challenges. |
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| Fast cycle scheme breaks bottlenecks
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2001-04-15 |
| The need for higher levels of performance was hampered by significant gaps between the speed of CPUs and their closely linked memories. Higher speed performance can be achieved by treating the memory unit as a quasi-multibank configuration. |
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| Leveraging PLDs for embedded system functionality
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1999-03-01 |
| You can directly apply the techniques and tools used in Internet Reconfigurable Logic (IRL)-based enterprise development to embedded systems and thus enhance their capabilities. |
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| Computers of the next millennium: Unplugged
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1999-12-22 |
| My daughter is fairly computer literate and does not give much thought to the Y2K problem or the possibility of computers/software failing at the end of the millennium. But my wife lives in terror, fearing that planes will fall out of the sky, power utilities will fail (not mention computer banking systems), and even the |
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| New formula to speed up PCB designs
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2008-05-16 |
| PCB designers need a methodology that helps them avoid design iterations between the design and layout stages, or finding issues with the board in the lab with a physical prototype. Hemant Shah of Cadence Design Systems discusses how a "correct-by-construction" PCB layout methodology can help PCB designers shorten their design cycle. |
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