Using parallel-distributed HDL simulation
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1999-10-01 |
| Parallel-distributed simulations can reduce the time required to perform HDL simulations without dramatically affecting existing design flows. While the theoretical limit of parallel simulations is not reached, the simulation times do approach the limit within reason |
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| Accelerate design performance with HDL coding practices
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2006-03-16 |
| Improve design performance by writing an HDL code that is efficient for your targeted device |
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| EDA Consortium tackles FPGA productivity
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2001-06-16 |
| The recent EDA Consortium tackled important issues that focus on direct HDL entry and better productivity measurements for designers and engineers |
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| Extend peripheral set of embedded processors
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2004-12-01 |
| System designers define and integrate peripheral subsystems without writing HDL using the SOPC Builder tool |
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| Automating rules check for safety-critical design
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2010-12-27 |
| Learn how automating rules checking can save time and resources, and possibly even provide certification credit. |
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| Long road ahead for analog synthesis
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2000-05-01 |
| It may be a bit like asking why can't women be more like men, but the question, "Why can't analog be more like digital?" is the most common complaint among engineers attempting to use analog design tools. Synthesis (the automatic generation of physical circuitry from a high-level language description) is one area where analog design departs drastically from digital. |
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| Perform integrated HW/SW verification
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2008-01-02 |
| As the lines marking the responsibilities of HW/SW teams and who is responsible for implementation and debug are getting blurred, new methodologies must be adopted to effectively validate an entire IP or silicon solution. The ability to efficiently and optimally design, and perform system-level verification can result in a significant competitive advantage, especially as software solutions become expected deliverables along with complex IP or silicon. |
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| Syntax raises RTL abstraction level
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2001-05-16 |
| A University of Toronto professor has proposed a new RTL abstraction syntax that he claimed can be implemented by a modest extension to traditional imperative programming languages. |
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| Mentor CEO argues FPGAs will drive platforms
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2001-05-01 |
| This article describes how FPGA platforms will innovate designs and how engineers can make the most out of it. |
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| Programmable system chips move forward
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2001-05-01 |
| Using dedicated hardware to boost real-time performance of embedded systems is a common practice and, with the introduction of PSCs, software engineers will learn how to boost performance of timing-critical software functions. |
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| Optimizing ASIC design flow for SoPCs
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2001-05-01 |
| System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly. |
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| Speed enhancements for Model Tech upgrades
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2001-04-15 |
| This article discusses the ModelSim simulation upgrade, which promises faster performance, better memory use, new interactive debug features and improved testbench and regression test support. |
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| How to reset an FPGA
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2011-08-22 |
| Know the various reset options available for FPGAs, as well as their advantages and disadvantages. |
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| Accelerate processor verification through testbench infrastructure reuse
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2011-09-01 |
| Find out how specialised processor verification IP can eliminate historical development and maintenance commitments. |
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| Dolphin, Raisonance team-up on microcontroller core
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2001-06-01 |
| The Dolphin Integration and Raisonance team up to create a hierarchical development system for the 8051 8-bit microcontroller core is expected to bring enhancements in the field of control technology. |
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| Overcome challenges of ASIC/SoC prototyping with FPGAs
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2011-10-24 |
| Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy. |
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| Verification firm starts partners program
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2001-04-15 |
| Seeking deeper integrations with third-party EDA tools, Verisity Design Inc. announced its Verisity Interoperability Partners (VIP) program. This technical article discusses that program and its effect to the EDA industry. |
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| Analog, mixed-signal design flow found wanting
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2001-06-16 |
| Different views cloud the current analog/mixed-signal design flow issue and should stop concentrating on the problem but find a lasting solution for the industry to further prosper. |
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| Speeding up medical imaging process using FPGA
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2011-09-01 |
| Read about the use of FPGA platform and a synthesis tool called Impulse C to speed up a statistical line of reaction estimation for a high-resolution PET scanner. |
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| Equivalence checking for SoC blocks
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2001-11-16 |
| This technical article explains that as custom blocks become increasingly important for SoCs, equivalence checking between transistor-level implementation and behavioral modeling become equally significant design factors. |
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| FPGA tools need hardware assistance
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2001-05-01 |
| While techniques such as logic emulation provide a new tool for logic designers, many other FPGA-based systems serve as high-performance replacements for standard computers. |
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| Transaction-based simulation using SystemC/SCV
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2005-03-16 |
| Learn how SystemC/SCV speeds up simulation and verification cycles to provide overall project cycle with better quality results |
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| Verification tech captures automotive expertise
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2005-09-01 |
| The automotive industry calls for modern verification techniques as the proliferation of electronic gadgetry adds to rising IC complexity in cars |
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| Formal verification for IP soft core
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2003-11-17 |
| Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them. |
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| One approach for debugging of modified designs
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2001-03-01 |
| Two engineers describe a methodology of comparing old designs to new designs in order to validate the new one. |
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| Hardware/Software co-development and SoC verification
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1999-09-01 |
| Different tools and methods are needed to address system-level architecture, hardware/software co-development, and full verification of SoCs in their target environments. Rather than inventing new solutions, leverage techniques proven in the PCB systems world. |
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| Solving problems early on using co-verification
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2004-11-16 |
| Learn the importance and benefits of hardware and software co-verification before the physical design becomes available. |
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| The need for board-level simulation
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2000-11-01 |
| No longer just an option, board-level simulation is a necessity for most of today's designs. |
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| Developing a video emulation environment
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2002-01-01 |
| This technical article describes the relevance of employing verification and emulation to video communications design and the IC capable of providing standards-based motion video encoding and decoding for real-time video conferencing apps. |
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| Recycle RTL testbenches to verify IP models
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2003-09-01 |
| Future work in the area of reusing RTL testbenches to verify TLM blocks will focus on fully automating the process, including automatic fault checking. |
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