The advantage of using logic BIST for ASIC designs
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2000-12-01 |
| This technical paper reveals the advantage of using logic BIST for ASIC designs |
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| Optimizing ASIC design flow for SoPCs
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2001-05-01 |
| System-on-programmable-chip technology has characteristics of both board-based design and ASIC-based SoC design. The immediate attraction of SoPC is that the design can be up and running very quickly |
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| Evaluating MEMS, ASIC chips for automotive apps
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2009-07-31 |
| This article describes the technical challenges related to automotive electronics qualification and verification of a MEMS-based sensor and ASIC system |
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| Using ISSP technology in structured ASIC design
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2003-12-16 |
| NEC's ISSP technology for designing structured ASIC has become popular with design engineers because of its easy-to-use design flow and clear road map for 90nm |
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| Overcome challenges of ASIC/SoC prototyping with FPGAs
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2011-10-24 |
| Learn about FPGA-based prototyping and the various factors that must be taken into account to successfully implement a prototyping strategy. |
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| ASIC generation revamped for IP reuse
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2001-06-01 |
| For designers, the linchpin for complete IP reusability is the programmable VLIW processor core, along with programmable buses and interface ports. |
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| Adapting ASIC designs for use with Spartan FPGAs
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2000-03-20 |
| This paper describes a new family of integrated switchers that build on the simplicity of switchers like TOPSwitch but add numerous features without the associated cost. It describes a family of devices that incorporate soft-start, under-voltage lock-out, over-voltage lockout, external current limit, frequency jitter and other features, all incorporated into a single 5-pin package. |
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| A new ASIC technology for mid-volume quantities
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2003-02-03 |
| NEC is giving customers the option of using ISSP, claiming to be the ideal solution for customers wanting high-performance ASICs, but only in small to mid-sized volumes. |
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| Standard metal enables paradigm shift in ASIC technology
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2005-08-16 |
| Deep-submicron design and manufacturing issues drive the critical need for a new design technology to replace standard cell |
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| Simplify automotive ASIC design with FMEA
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2011-01-10 |
| Learn about failure modes and effects analysis (FMEA), an essential tool to examine all aspects of a product specification. |
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| Using your wireless ASIC-AN18
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2004-05-13 |
| This app note shows that the P35-47-series of wireless ASICs are grouped into two families, the highly integrated transceiver ASICs and the amplifier/switch ASICs. |
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| Timing analysis tools greatly impacts a successful design
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2001-05-01 |
| Today, static timing analysis tools have matured to the point of handling significantly more complex design styles. This article examines the different kinds of timing analysis products used in ASIC, FPGA, and board-level design |
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| HomePlug brings cost-effective power line networking
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2001-12-16 |
| This article describes how Ethernet-class networks over standard home power lines are advancing in the industry due entirely to the prevalent presence of ASIC-based signal processors |
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| FPGAs take wrong road
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2001-04-01 |
| FPGA vendors are gobbling up design starts that have been marginalized by the ASIC industry; the focus has led to massive improvements in routing resources, and addition of embedded SRAM and CPUs |
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| Shorten test time with package-based MBIST strategy
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2010-08-02 |
| Test time is a significant component of ASIC cost. It needs to be minimized and yet has to have maximum coverage to ensure zero-defect scenario for an automotive application |
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| Hardware implementations of multi-rate digital filters
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2001-04-01 |
| It is important to efficiently map interpolation and decimation functions into hardware. Here is a look at DSP, PLD, and ASIC implementations for multi-rate filters |
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| Taking new stabs at programmable analog
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2000-03-01 |
| Programmable logic has some traditional advantages over ASIC design. The gate count of FPGAs approaches that of custom circuits. FPGAs can be programmed—and re-programmed—out in the field, enabling fast time to market. ASICs, in comparison, need careful attention to layout and fabrication technology. It can take anywhere from six weeks to two years (depending on the complexity of the circuit) to get an ASIC working properly |
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| A New Way To Design ASICs
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2001-03-30 |
| This paper presents a new way to design ASICs that dramatically reduces the cost of ASIC development and greatly decreases the time needed to bring a successful design to market |
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| Timing closure: Hybrid optimization to the rescue
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2004-08-16 |
| Hybrid optimization combines ASIC cell-based design flow with transistor-level optimization to achieve improvement in timing closure |
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| Vendors must support IP reuse in SoC
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2003-04-16 |
| The need for IP reuse will increase as design complexity grows to higher levels. This support structure forms an invisible layer that would make SoC/IP-ASIC engagements as seamless as possible |
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| Reducing fault-coverage analysis with DFT, Part 2
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2002-04-01 |
| This technical paper is the second of a two-part discussion wherein the author considers fault-coverage analysis and simulation for full-scan testing of ASIC designs |
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| Choosing the right design flow model with integrated architecture
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2004-02-02 |
| Users of ASIC, COT and COPD models are finding that flows based on an integrated RTL-to-GDSII system can offer additional benefits when fully leveraged |
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| Bluetooth Enabled ASICs Versus Standard Bluetooth Chipsets
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2001-07-02 |
| This paper discusses the pros and cons of using commercially available Bluetooth chipsets and integrating Bluetooth functionality into an existing ASIC |
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| Ease automotive graphics design
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2008-05-16 |
| Says Kerry Howell of Lattice Semiconductor, when automotive graphics designers use a standard ASSP or a custom ASIC as the controller, they encounter a few speed bumps on the road to system implementation. The versatile nature of FPGA devices, plus commercially available intellectual property, allows for the integration of almost all the graphics system functions in one device |
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| Diagnostic test for design validation
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2004-04-16 |
| Whether you are testing a new MCU or an ASIC, post-silicon validation of the design is a must. Here's a look at diagnostic tests and techniques |
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| Programmable logic: Proving ground for Gigabit Ethernet switch
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1999-06-29 |
| This article focuses on the use of PLDs to implement large subsystems within a single chip and its integration to existing design flows. In discussing these issues, the paper uses the example of the network processing ASIC called Argus |
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| Shrink current transducers with Hall-effect sensor integration
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2008-10-16 |
| The trend in power electronics is no different from other fields: greater integration and lower component count. The development of an ASIC is one of the first steps toward miniaturization |
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| System specs drive multiprocessor SoC
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2002-02-16 |
| SoC design requires new tools and a different skill set than traditional ASIC chip design. The case study illustrates new challenges and describes methodologies to address them |
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| Customizable MCUs take on FPGA tasks
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2007-11-01 |
| Using a customizable MCU with an MPCF allows designers to integrate their custom IP into a near off-the-shelf solution. It offers the cost, power consumption and performance benefits of a full-custom ASIC, with NREs and design cycle that are not much different from those of an off-the-shelf MCU + FPGA design |
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| Reducing fault-coverage analysis with DFT
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2002-03-16 |
| This technical article is the first of two parts that considers how fault-coverage analysis and simulation for full scan testing of ASIC designs are equally applicable to other types of IC design, chiefly of which are FPGAs |
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