Taking GALS to 65nm designs
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2004-11-16 |
| Emerging globally asynchronous, locally synchronous SoC design architectures offer a powerful way to solve interconnect issues in these superintegrated chips. |
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| Drive parametric yields higher at 65nm, beyond
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2007-10-01 |
| The need to characterize and model intrinsic variability in a production-worthy process will intensify and represent a new imperative for improving yield in 65nm process technologies and beyond. A PAM platform methodology can foster a collaborative environment between design and manufacturing, a condition key to driving parametric yields higher |
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| Implement low-power 65nm FPGA designs
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2007-04-16 |
| This article explores the benefits of reduced power consumption. It also illustrates the many process and architectural innovations implemented in Virtex-5 devices. |
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| Developing macrocell libraries in CMOS
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2005-09-16 |
| The Crolles2 Alliance brings resources together to develop macrocell libraries in 90nm and 65nm CMOS technologies |
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| Conquer loss, create high-yielding designs
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2007-03-01 |
| This article discusses the three most important yield-loss mechanisms in 65nm designs, and proposed methods for mitigating yield loss without severe impact on design schedules. Using tools that are both powerful and well-integrated, design and layout engineers can create high-yielding designs while meeting design specifications and demanding schedules |
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| Rethinking DFT strategies in nanometer designs
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2007-06-18 |
| As the industry races to the 90nm and 65nm nodes, manufacturers are exploring more advanced tests, a 'complete' solution with the most advanced test patterns and fault models needed to improve defect detection |
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| Targeting small delay defects
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2010-01-13 |
| To maintain the quality of test for the reasonable DPM levels, more and more test engineers are looking to target small delay defects with ATPG. |
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| Address challenges in 40G/100G SerDes design, implementation
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2011-11-17 |
| Read about the various aspects of SerDes design such as transmit/receive portions. |
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| Benefits of SONOS memory for embedded flash
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2011-10-13 |
| Here's a discussion on why silicon-oxide-nitride-oxide-silicon memory technology is ideally suited for eFlash. |
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| Win the mobile TV design challenge
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2008-02-18 |
| According to Lionel Federspiel of Infineon Technologies: in reviewing mobile TV technology trends, one needs to differentiate between product feature set, packaging, performance, semiconductor processes used and most importantly, the RF receiver performance. |
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| 'Design-with-test' for low-power devices
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2007-01-16 |
| A new methodology called design with test in which tools are deeply integrated and power consumption is highly considered during testing will be key in ensuring the continued success of low-power products. |
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| Obtain best performance from your FPGA design
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2007-01-01 |
| This article will explore how FPGA designers can benefit from the latest FPGA building blocks in their quest for higher system-level performance. |
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| Optimizing performance, power in 90nm FPGAs
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2005-10-03 |
| The industry has crossed an inflection point at 90nm, where performance competes with power and thermal budgets |
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