Board and interface design for AutoBahn Spanceiver (MC100SX1451FI50/100
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2000-12-07 |
| This application note provides detailed information about board design and interface circuits for the AutoBahn Spanceiver |
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| Design alternatives for the basic user input device interface in portable systems
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1999-10-30 |
| This paper will investigate the different approaches in the design of the User Input Device Interface, taking into account the unique requirement of UIDs in portable systems, and will point out the advantages and disadvantages of each approach |
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| SanDisk CompactFlash & Motorola 8bit microcontroller interface design reference example
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1999-10-28 |
| The choices and modes for accessing and configuring the SanDisk CompactFlash cards are described in this note. |
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| Dual DIMM DDR2 SDRAM memory interface design guidelines
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2007-03-05 |
| As applications become more demanding, deeper memory is required leading to the need for more than one DIMM memory configuration. This application note focuses on the system implementation of a dual unbuffered DIMM DDR2 SDRAM memory interface, operating at 267MHz/533Mbps |
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| V5 access network interface design using MT9075
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1999-10-19 |
| This application note discusses the use of the V5 interface to either the Access Network or the Local Exchange to enable a network operator to use the access equipment from any vendor conforming the V5 interface specifications |
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| CompactFlash and 8260 interface design guide
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2002-05-09 |
| This application note describes a possible interface between a CompactFlash card and Motorola's MPC8260 microprocessor |
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| ACCEL-To-SPECCTRA interface and design language translation
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2001-05-28 |
| This application note describes the background involving the interface between ACCEL EDA and Specctra |
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| ISP1581 USB 2.0 Scanner using ASIC from Service & Quality Technology Co. Ltd
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2003-05-27 |
| This application note provides details on how to implement the USB 2.0 scanner design using the ISP1581 high-speed USB 2.0 interface device together with the SQ009 ASIC from Service & Quality Technology |
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| ORCA series 3 microprocessor interface
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2002-09-05 |
| This application note discusses the various uses of the ORCA series 3 FPGA system for embedded microprocessor interface design |
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| Designing a DSP system
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2001-10-12 |
| This application note describes various aspects of DSP system design such as interfacing A/D and D/A converters, DAQ techniques (Busy-Polling, Interrupts, DMA), control interface design, memory considerations, and development systems |
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| Configuring Spartan-II FPGAs from parallel EPROMs
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2001-04-12 |
| This application note describes a simple CPLD-based interface design to configure a Spartan-II device from a parallel EPROM using the Slave Parallel configuration mode |
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| Single Ended and Single Power Supply Hybrid Circuit
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2000-04-13 |
| This application note introduces a simple hybrid circuit that will save costs as well as provide high performance in power supply interface design. It highlights transmission and reception features along with PCB guidelines and details on parameters such as output level |
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| IOM-2 interfacing on TMS320C54x
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2001-04-30 |
| This application note describes an interface design for connecting the synchronous serial port of Texas Instruments' TMS320C54x DSP to an IOM-2 serial bus |
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| The TMS320C54x DSP HPI and PC parallel port interface
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2001-05-02 |
| This application note describes the hardware interface design between the host (PC parallel port in the bi-directional mode) and the HPI (host port interface) using TI's TMS320C54x DSP |
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| High-speed ADC THS1041and FPGA interface considerations
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2007-05-04 |
| The THS1041 from Texas Instruments is a 10bit, 40MSPS, high-speed ADC. For many years because of its low power dissipation and extended life, it has been used in various applications such as programmable gain amplifier and built-in clamp. With recent FPGA development, some application systems have been upgraded with a direct interface of the THS1041 to an FPGA, for example, by connecting I/O pins of the THS1041 to the I/O pins of Xilinx Spartan-3 or Altera PLD. For such an interface, a power-on initial state should be considered in the interface design. Otherwise, the power-on initial state of the FPGA can affect the initial state of THS1041 and in some cases, affect the entire application system. In order to ensure the successful interfacing of the THS1041 to an FPGA, a test was conducted, and this application report presents those results |
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