Hints, tips and tricks for using XABEL with Xilinx M1.5 design and implementation tools
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2000-06-29 |
| This application note summarizes the issues and design techniques specific to the Xilinx ABEL Interface, version M1.5 |
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| Pericom FCT logic for hot-plug applications
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2000-11-29 |
| This application note discusses how Pericom FCT devices can be successfully used as an interface between a host system and a hot-plug module as well as some important related design considerations |
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| Adding external data memory to the Z893X1 DSP chip
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2000-09-08 |
| This application note addresses the data memory insufficiency of Zilog's Z893X1 DSP by adding a simple external data interface, and presents some possible design variations |
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| RSDS Flat Panel Display Design Guidelines Part 1
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2002-11-08 |
| This application note describes the use of RSDS interface technology in flat panel display design to reduce power, size, and component count |
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| Interfacing ISP1161 to Motorola DragonBall EZ RISC processor
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2003-05-27 |
| This application note deals with the critical issues in ISP1161 single-chip USB host and interface device controller's embedded design, using the Motorola DragonBall-EZ RISC processor as an example |
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| Considerations when using the 66 MHz 21150 as an accelerated graphics port-peripheral component interconnect bridge
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1999-12-13 |
| This document compares the PCI Local bus specification, Revision 2.1 and the AGP interface specification, Revision 2.0 as they apply to the 21150 PCI-to-PCI bridge. It highlights the relevant differences between these specifications, and indicates potential design issues where careful design considerations are warranted |
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| ISP1581 Mass Storage Kit Firmware programming guide
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2002-11-20 |
| This application note discusses a firmware design that will enable the ISP1581 USB 2.0 interface device to achieve the fastest transfer rate over USB |
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| MB86930 SPARClite DRAM CONTROL INTERFACE
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1999-12-10 |
| This application note outlines the design used on the Fujitsu SPARClite Evaluation Board to interface the MB86930 with the DRAM subsystem. The main objective of the paper is to show the simplicity of the external design requirements, while achieving high performance of three CPU cycle page mode access at 40MHz |
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| Drive ESCON with HOTLink
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2001-03-22 |
| This application note contains an overview of ESCON (Enterprise System CONnection) operation and a design example of ESCON physical interface implemented using HOTLink and a pASIC FPGA |
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| TMS320C54x interface with SDRAM
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2001-05-15 |
| This application note provides a comprehensive guide for the design of the hardware interface between Texas Instruments' TMS320C54x DSP and the TMS626812A SDRAM using FPGAs |
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| DataLink configuration guide for DL2000-K2F dual port DF1 to DH+
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2001-09-04 |
| This application note contains configuration, system design and programming information on the DL2000-K2F Dual Serial Port DF1 to DH+ interface |
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| Implementing DDR2-400 memory interfaces in Spartan-3A FPGAs
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2008-06-09 |
| High-performance consumer products and their requirement for low-cost, high-bandwidth memory create demand for high-performance DDR2 memory interfaces. Xilinx offers a Memory Interface Generator (MIG) integrated in the CORE Generator software for ultimate design flexibility and ease-of-use |
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| Interfacing 93CX6 Serial EEPROMs to PIC16C5X Microcontrollers
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2000-06-07 |
| This application note is intended for design engineers who wish to incorporate a pre-packaged serial EEPROM interface driver into their application |
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| Interface circuits for TIA/EIA-485 (RS-485
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2007-05-04 |
| This article provides information concerning the design of TIA/EIA-485 interface circuits. The document discusses the need for balanced transmission-line standards and gives an example for a process-control design. Line loading is discussed with subtopics of signal attenuation, fault protection and galvanic isolation. Finally, setting up and measuring using eye patterns is documented. Eye patterns are used to measure the effects of signal distortion, noise, signal attenuation, and the resultant intersymbol interference in a data transmission system |
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| Improving memory access timing in Z182 applications
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1999-10-01 |
| This application note demonstrates the calculations of both ROM and RAM access timing, and provide examples of a conventional processor/memory interface design for V.FAST modem with processing speeds approaching 33MHz |
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