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Ultra-fast synchronous counters 2000-06-22
This application note discusses the implementation of a fully synchronous, non-loadable, binary counter by using the XC4000 and XC3000 FPGA designs  
CPLD timing 2008-09-05
In this application note we will discuss how to constrain a CPLD design and how to verify that the design has met timing. Fundamentally, CPLD timing is the same as FPGA timing; however, the CPLD timing constraints are a subset of the FPGA timing constraints  
ORCA series 3 programmable clock manager (PCM) 2002-12-06
This application note describes the modes of operation for the programmable clock managers of the ORCA series 3 FPGA  
High-speed, loadable 16-bit binary counter 2000-09-01
This application note demonstrates how to implement the AT6000 Series FPGA as a fast synchronous, loadable 16-bit binary counter that operates at 70MHz on and off chip under the worst commercial operating conditions  
An overview of multiple CAM designs in Virtex family devices 2001-04-12
This application note provides an overview of multiple CAM (Content Addressable Memory) designs in Xilinx Virtex FPGA family  
Configuring Xilinx FPGAs using an XC9500 CPLD and parallel PROM 2001-04-12
This application note describes a simple, low-cost design to configure any Xilinx FPGA in a serial configuration mode using a Xilinx XC9500 CPLD and any parallel PROM  
Using SelectI/O interfaces in Spartan-II FPGAs 2001-04-12
This application note describes how to take full advantage of the flexibility of the Spartan-II FPGA family's SelectI/O features and the design considerations to improve and simplify system-level design  
16-bit up/down counter/shift register 2000-09-01
This application note demonstrates how to implement the AT6000 Series FPGA as a synchronous, 16-bit up/down counter/shift register that operates at 22MHz under the worst commercial operating conditions  
Efficient 8X oversampling asynchronous serial data recovery using IDELAY 2007-04-02
Xilinx Virtex-4 and Virtex-5 devices a have high-precision programmable delay element associated with every input pin. These delay elements, called IDELAY, can be used to implement an oversampler that uses very few FPGA logic resources and, more importantly, just a single DCM and two global clock resources to do 8X oversampling. This solution provides better jitter tolerance than techniques that use multiple DCMs  
Using a Dallas Semiconductor DS1075 EconOscillator to clock an 8051 microprocessor 2001-04-06
This application note discusses how Dallas Semiconductor's DS1075 EconOscillator chip can be used for various types of clocked logic, such as microprocessor, FPGA and CPLD circuits  
Indirect programming of SPI Serial flash PROMs with Spartan-3A FPGAs 2008-09-16
This application note describes the hardware setup, file generation flow, and software flow for programming an STMicroelectronics M25Pxx SPI configuration PROM through the JTAG interface of a Spartan-3A FPGA using iMPACT 9.1.01i. The software flows, including PROM  
Emulation flow for Xtensa cores 2008-09-01
This application note explains how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system  
Custom PCI timing budgets for Spartan-3 generation FPGAs 2008-05-26
The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices. The provided example applies this information to a design using Xilinx Spartan-3 Generation FPGAs with Xilinx LogiCORE PCI interfaces  
Web server reference design using a PowerPC-based embedded system 2004-12-09
This app note details an embedded system example design of a web server running on a PowerPC core within a Xilinx Virtex-II Pro FPGA  
Using a microprocessor to configure Xilinx FPGAs via Slave Serial or SelectMAP Mode 2008-09-13
This application note provides a thorough discussion of FPGA configuration via a microprocessor, covering Virtex and Spartan FPGA families. Also, this application note presents a system-level model using a Xilinx CPLD to implement an interface to the FPGA configuration pins  


EE Times India - Total Search 787 Articles
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Free circuits roll for LTE basestations on FPGA 2008-11-26
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