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EE Times Asia - Total Search 168 Articles Sort by date Sort by relevance
Ultra-fast synchronous counters 2000-06-22
This application note discusses the implementation of a fully synchronous, non-loadable, binary counter by using the XC4000 and XC3000 FPGA designs  
System design with new XC4000X I/O features 2000-06-26
This application note examines the I/O features of the XC4000X FPGA family including an additional latch on each input and an output multiplexer on each output. These features are discussed, and examples show how to use them  
A guide to using field programmable gate arrays (FPGAs) for application-specific digital signal processing performance 2000-06-22
This application note describes the benefits of using an FPGA as a DSP coprocessor, as well as, a stand-alone DSP engine. Two case studies, a Viterbi decoder and a 16-Tap FIR filter are used to illustrate how the FPGA can radically accelerate system performance and reduce component count in a DSP application  
Drive ESCON with HOTLink 2001-03-22
This application note contains an overview of ESCON (Enterprise System CONnection) operation and a design example of ESCON physical interface implemented using HOTLink and a pASIC FPGA  
Clear Logic LIBERATOR design models 2002-06-12
This application note presents the Clear Logic LIBERATOR Verilog design model, which allows designers to prototype and change the design quickly through the use of an FPGA  
Configuration quick start guidelines 2002-06-28
This application note discusses the configuration and programming options for Xilinx's CPLD, FPGA, and PROM families, and lists some of the most popular configuration methods for each family  
I/O characteristics of the 'XL FPGAs 2000-06-20
This application note describes I/O parameters of the 'XL FPGA family in analog terms, giving the designer a better understanding of the circuit behavior  
16-bit four-to-one multiplexer with 15ns delay 2000-09-01
This application note demonstrates how to implement the AT6000 Series FPGA as a 16-bit four-to-one multiplexer with a 15ns delay from the select control to the most significant output bit  
Analog devices TigerSHARC link 2004-12-09
This app note demonstrates a full-featured transmitter/receiver macro that can communicate with Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGA families via the analog devices ADSP-TS101S TigerSHARC link-port function  
High-speed, loadable 16-bit binary counter 2000-09-01
This application note demonstrates how to implement the AT6000 Series FPGA as a fast synchronous, loadable 16-bit binary counter that operates at 70MHz on and off chip under the worst commercial operating conditions  
Connecting Xilinx FPGAs to Texas Instruments ADS527x series ADCs 2004-12-10
This app note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex-II or Virtex-II Pro FPGA  
CPLD timing 2008-09-05
In this application note we will discuss how to constrain a CPLD design and how to verify that the design has met timing. Fundamentally, CPLD timing is the same as FPGA timing; however, the CPLD timing constraints are a subset of the FPGA timing constraints  
Custom PCI timing budgets for Spartan-3 generation FPGAs 2008-05-26
The information presented in this application note is applicable to any embedded PCI implementation using Xilinx FPGA devices. The provided example applies this information to a design using Xilinx Spartan-3 Generation FPGAs with Xilinx LogiCORE PCI interfaces  
Spartan-3A DSP S3D1800A starter platform features and functions 2008-05-26
The Spartan-3A DSP S3D1800A Starter Platform highlights the unique features of the Spartan-3E FPGA family and provides a convenient development board for embedded processing applications  
Emulation flow for Xtensa cores 2008-09-01
This application note explains how to map an Xtensa or Diamond core to an FPGA with a minimal on-chip system  


EE Times India - Total Search 727 Articles
MCU kit consumes less active power 2008-09-03
FPGA, CPLD vendors eye automotive sector 2008-09-01
Actel outlines PLD strategy 2008-08-26
Arrow incorporates ARM processors into Altera FPGAs 2008-08-26
Altera, Mentor partner on DO-254 2008-08-21
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