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EE Times Asia - Total Search 186 Articles Sort by date Sort by relevance
IEEE 1149.1-1990 standard test access port and boundary-scan 2000-09-05
This application note demonstrates how the AT6000 Series FPGA can be programmed with the 1149.1 standard test logic and then reprogrammed for normal operation when the system or board diagnostics are complete  
Using the Virtex delay-locked loop 2000-06-26
This application note demonstrates how to use the Virtex FPGA Series' four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits to implement several circuits that improve and simplify system-level design  
Using the Virtex Block SelectRAM+ 2000-06-23
This application note demonstrates how to utilize the Virtex FPGA Series' dedicated blocks of on-chip 4.096kb dual-port synchronous RAM by using each port of the block SelectRAM+ memory independently as a read/write, read or write port, and configure each port to a specific data width  
ORCA series 3 programmable clock manager (PCM) 2002-12-06
This application note describes the modes of operation for the programmable clock managers of the ORCA series 3 FPGA  
Configuration quick start guidelines 2002-06-28
This application note discusses the configuration and programming options for Xilinx's CPLD, FPGA, and PROM families, and lists some of the most popular configuration methods for each family  
Building high performance FIR filters using KCMs 2000-06-23
This application note demonstrates the XC4000E FPGA as an ideal solution to high-performance FIR filter implementation with the inherent advantage of re-programming to optimize the available gates in the form of Constant (K) Coefficient Multipliers (KCM  
Memory interface appnotes overview 2007-03-12
This document provides an overview of all Xilinx memory interface application notes that support Virtex series and Spartan series FPGAs. In addition, some key features of the prevalent memory technologies are also provided. For each application note, the data capture technique, clocking scheme, FPGA resources used, and supported memory technology are described briefly  
Using Suspend Mode in Spartan-3 Generation FPGAs 2008-09-13
The Spartan-3A, Spartan-3AN, and Spartan-3A DSP FPGA families offer an advanced static power management feature called Suspend mode, which reduces FPGA power consumption while retaining the FPGA’s configuration data and maintaining the application state. The device can quickly enter and exit Suspend mode as required in an application  
Connecting Xilinx FPGAs to Texas Instruments ADS527x series ADCs 2004-12-10
This app note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex-II or Virtex-II Pro FPGA  
Tips for successful power-up of today's high-performance FPGAs 2005-06-10
This app note explains FPGA power requirements and the causes of their power-up problems  
Digital frequency/Phase comparator (DFPC) 2000-09-01
This application note demonstrates how to implement the AT6000 Series FPGA as a digital frequency/phase comparator (DFPC) that interfaces to a voltage-controlled oscillator (VCO  
Boundary scan in XC4000 and XC5200 series devices 2000-06-23
This application note describes the boundary-scan facilities in the XC4000 and XC5200 Series FPGAs, and explains how boundary scan is incorporated into an FPGA design  
Ultra-fast synchronous counters 2000-06-22
This application note discusses the implementation of a fully synchronous, non-loadable, binary counter by using the XC4000 and XC3000 FPGA designs  
Clear Logic LIBERATOR design models 2002-06-12
This application note presents the Clear Logic LIBERATOR Verilog design model, which allows designers to prototype and change the design quickly through the use of an FPGA  
Designing telecommunication applications using digital signal processing functions with FPGAs 1999-11-26
This paper describes the use of a DSP targeted to Actel's A32200DX FPGA (Field Programmable Gate Array). It also describes the techniques that can be applied to similar applications customizing and reuse of the VHDL cores  


EE Times India - Total Search 747 Articles
Interfacing LVPECL devices to FPGAs 2008-10-06
Say goodbye to remote controls 2008-10-03
PCIe XMC offers obsolescence-proof design 2008-10-01
Building Xtensa-based emulation system on Xilinx FPGA 2008-09-29
AMC module features 32-bit FIFO per channel 2008-09-26
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