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Configuration issues: Power-up, volatility, security, battery back-up 2000-06-28
This application note covers several related configuration subjects including: the power up details of Xilinx FPGAs; Xilinx FPGA reaction to power-supply glitches; danger of picking up erroneous data and configuration; ways to maintain configuration during loss of primary power; and ways to secure a design against illegal reverse engineering  
Computing multidimensional DFTs using Xilinx FPGAs 2000-03-23
This application note reports on a reconfigurable computing architecture that takes advantage of the reduced computational requirements of the polynomial transform method for computing 2D DFTs. A FPGA architecture is described. The device is capable of processing 24,512-by-512-pixel images per second  
16-bit carry-select adder 2000-09-01
This application note demonstrates how to implement the AT6000 Series FPGA as a carry-select adder, which achieves speeds up to 40 percent faster by performing additions in parallel and reducing the maximum carry path  
Designing telecommunication applications using digital signal processing functions with FPGAs 1999-11-26
This paper describes the use of a DSP targeted to Actel's A32200DX FPGA (Field Programmable Gate Array). It also describes the techniques that can be applied to similar applications customizing and reuse of the VHDL cores  
Configuration quick start guidelines 2002-06-28
This application note discusses the configuration and programming options for Xilinx's CPLD, FPGA, and PROM families, and lists some of the most popular configuration methods for each family  
644MHz SDR LVDS transmitter/receiver 2002-06-28
This application note describes single data rate transmitter and receiver interfaces operating up to 644MHz, using 17 LVDS pairs, implemented in a Virtex-II FPGA  
Using the Virtex delay-locked loop 2000-06-26
This application note demonstrates how to use the Virtex FPGA Series' four fully digital dedicated on-chip Delay-Locked Loop (DLL) circuits to implement several circuits that improve and simplify system-level design  
Edge detection in AT6000 FPGAs 2000-09-05
This application note presents a reference design of a fully pipelined bit-parallel edge detection circuit that utilizes only pipelined adders and fits into one AT6010 FPGA  
Analog devices TigerSHARC link 2004-12-09
This app note demonstrates a full-featured transmitter/receiver macro that can communicate with Spartan-II, Spartan-IIE, Spartan-3, Virtex, Virtex-E, Virtex-II, and Virtex-II Pro FPGA families via the analog devices ADSP-TS101S TigerSHARC link-port function  
8-bit, S-P/P-S "corner-bender" data converter 2000-09-01
This application note demonstrates how to implement the AT6005 FPGA device in two S-P/P-S corner-bender circuits: one optimized for area and power consumption, the other for speed and expandability  
Connecting Xilinx FPGAs to Texas Instruments ADS527x series ADCs 2004-12-10
This app note describes how to connect a high-speed Texas Instruments (TI) ADS5273 analog-to-digital converter (ADC) with serialized LVDS output to a Virtex-II or Virtex-II Pro FPGA  
Interrupt usage on FlexRay CC 2006-06-02
This application note describes the initialization and usage of FlexRay communication controller interrupts at the Fujitsu evaluation board FLEXRAY-FPGA-EVA-KIT-369  
Boundary scan in XC4000 and XC5200 series devices 2000-06-23
This application note describes the boundary-scan facilities in the XC4000 and XC5200 Series FPGAs, and explains how boundary scan is incorporated into an FPGA design  
The low-cost, efficient serial configuration of Spartan FPGAs 2000-06-21
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approach recommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size, and board space associated with the serial configuration circuitry  
Debugging designs using Clear Logic models 2002-06-12
This application note illustrates different methods of debugging FPGA designs through the use of the company's LIBERATOR Verilog design model  


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