ORCA Series 3 FPGAs Programmable I/O Cell (PIC): Logic, Clocking, Routing, and External Device Interface
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2002-12-11 |
| This application note describes the features and advantages of the ORCA Series 3 FGPA programmable I/O cell (PIC) |
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| Implementing barrel shifters using multipliers
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2004-12-09 |
| This app note discusses the Virtex-II family of platform FPGAs. |
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| Stratix III power management design guide
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2007-03-05 |
| This document provides recommendations and guidelines for power management system design in systems featuring Altera Stratix III FPGAs. |
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| Symmetrical 8-tap FIR filter Macro (FIR8S)
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2000-09-05 |
| This application note details the implementation of a 32-tap FIR Filter macro in the AT6000 series FPGAs. |
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| A quick JTAG ISP checklist
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2002-06-28 |
| This application note describes a short list of considerations needed for optimum performance of ISP designs. The considerations apply to Xilinx ISP device families. |
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| Physical interface to QDRII memories using Actel ProASIC 3E FPGAS
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2008-10-22 |
| This application note shows how to implement a physical interface to QDRII memories in Actel's ProASIC3E devices, as well as IGLOOe devices, and A3PE3000L device (ProASIC3L family). |
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| Temperature, voltage, and current calibration in Fusion FPGAs
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2008-10-06 |
| Actel Fusion mixed-signal FPGAs integrate configurable analog features, including I/Os, prescalers, lowpass filters, and an ADC, enabling customers to perform temperature, voltage, and current measurements in their applications. |
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| RocketIO X transceiver clock mode switcher for Virtex-II Pro X FPGAs
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2004-12-10 |
| This app note demonstrates a way to switch clocking modes without knowledge of a PMA attribute bus interface. |
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| Standard 8-tap FIR filter Macro (FIR8)
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2000-09-05 |
| This application note details the implementation of a standard 8-tap FIR filter Macro in the AT6000 Series FPGAs. |
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| Connecting Virtex-II devices to a 3.3V/5V PCI bus
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2002-06-28 |
| This application note describes how to connect Virtex-II and Virtex-II Pro devices to a 3.3V or 5V PCI bus. |
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| A flexible architecture to drive sharp two-way viewing angle and standard LCDs
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2007-03-05 |
| This paper discusses an innovative architecture based on FPGAs and soft-core embedded processors that supports both standard and two-way viewing LCD products. |
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| Dynamic reconfiguration
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2000-06-28 |
| This application note describes the procedures for reconfiguring the more traditional Xilinx FPGAs of the XC3000, XC4000, and XC5200 families. |
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| Data acquisition systems using cache logic FPGAs
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2000-09-01 |
| This application note describes Atmel's enabling Cache Logic technology to make adaptive hardware possible for Data Acquisition, Logic Analyzer, and other instrumentation products. |
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| 1:7 Deserialization in Spartan-3E FPGAs at speeds up to 666Mbps
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2007-03-12 |
| Spartan-3E devices are used in a wide variety of applications requiring 1:7 deserialization at speeds up to 666Mbps. This application note targets Spartan-3E devices in applications that require 4-bit or 5-bit receive data bus widths and operate at rates up to 666 Mbps per line with a clock at 1/7th the bit rate. This type of interface is commonly used in flat panel displays and automotive applications. |
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| TMS320C54x interface with SDRAM
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2001-05-15 |
| This application note provides a comprehensive guide for the design of the hardware interface between Texas Instruments' TMS320C54x DSP and the TMS626812A SDRAM using FPGAs. |
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