Configuring Xilinx FPGAs with SPI flash memories using CoolRunner-II CPLDs
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2004-12-10 |
| This app note describes a method to configure Xilinx FPGAs, such as Spartan-IIETM and Spartan-3TM FPGAs, using inexpensive small Serial Peripheral Interface (SPI) flash memories. |
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| Interfacing LVPECL devices to QuickLogic Eclipse and Eclipse-II FPGAs
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2008-05-22 |
| This application note discusses software implementation and board level issues when interfacing LVPECL devices with QuickLogic Eclipse FPGAs. |
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| Symmetrical 32-tap FIR filter Macro (FIR32S)
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2000-09-06 |
| This application note details the implementation of a symmetrical 32-tap FIR filter Macro in the AT6000 Series FPGAs. |
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| Symmetrical 16-Tap FIR filter Macro (FIR16S)
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2000-09-05 |
| This application note details the implementation of a 16-tap FIR Filter Macro in the AT6000 Series FPGAs. |
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| Virtex power estimator user guide
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2000-06-21 |
| This application note explains how to use the Power Estimator worksheet, which is used to calculate estimated power consumption for Virtex designs. This worksheet considers the design resource usage, toggle rates, I/O power, and many other factors in the estimation. |
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| JJ-20.11-compatible interface for the DS2155 and DS21455 SCTs
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2006-06-02 |
| This application note describes how the Dallas Semiconductor DS2155 or DS21455 single-chip transceiver can be used to create an interface that is compatible with the Japanese JJ-20.11 standard. |
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| SONET rate conversion in Virtex-II Pro devices
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2002-06-28 |
| This application note targets Virtex-II Pro designs that require the direct use of Rocket I/O transceivers in 16-bit mode. |
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| Data generation and configuration for Spartan series FPGAs
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2001-04-12 |
| This application note discusses various methods to configure Xilinx's series of Spartan FPGAs. |
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| Virtex series configuration architecture user guide
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2001-04-12 |
| This application note presents an overview of the Virtex series architecture by emphasizing data bit location in the configuration bit stream. |
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| Status and control semaphore registers using partial reconfiguration
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2000-06-29 |
| This application note demonstrates how to lock the LUT SelectRAM to specific locations, determine the corresponding frame of data in the .RBT (Rawbits) file, modify the LUT memory as desired, and re-write this frame into the chip. |
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| Adapting ASIC designs for use with Spartan FPGAs
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1999-12-21 |
| Pre-existing ASIC intellectual property can be adapted for use with Spartan devices by following a straightforward procedure. |
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| Synthesizable 143MHz ZBT SRAM interface
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2000-06-23 |
| This application note demonstrates a Virtex design that interfaces to megabytes of external high-speed ZBT (Zero Bus Turnaround) SRAM in order to provide interleaved read/write without wasteful turnaround cycles. |
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| Block Adaptive Filter
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2000-06-23 |
| This application note describes a specific design for implementing a high-speed, full precision, adaptive filter in the XC4000E/EX family of FPGAs. |
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| Synchronous and asynchronous FIFO designs
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2000-06-22 |
| This application note describes RAM-based FIFO designs using the dual-port RAM in XC4000-Series devices. Synchronous designs with a common read/write clock are described, as well as asynchronous designs with independent read and write clocks. |
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| Multiplexers and barrel shifters in XC3000/XC3100
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2000-06-27 |
| This application note provides guidance for implementing high-performance multiplexers and barrel shifters in XC3000 LCA devices. |
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