Pulse-width modulation in Xilinx programmable logic
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2000-06-26 |
| This application note demonstrates how to build a variable PWM waveform using a counter and a storage register. |
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| Verification of prototype-board schematics
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2005-02-01 |
| Learn how to achieve schematic verification by slightly modifying the DUT verification environment. |
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| ORCA Series 4 I/O User's Guide
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2002-12-11 |
| This application note outlines a user guide for the I/O operation of the ORCA Series 4 of FPGAs. |
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| 170MHz FIFOs Using the Virtex Block SelectRAM+
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2000-06-26 |
| This application note describes a way to create a common-clock (synchronous) version and an independent-clock (asynchronous) version of a 512-by-8 FIFO, with the depth and width being adjustable within the Verilog code. |
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| TMS320C54x interface with SDRAM
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2001-05-15 |
| This application note provides a comprehensive guide for the design of the hardware interface between Texas Instruments' TMS320C54x DSP and the TMS626812A SDRAM using FPGAs. |
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| Estimating the performance of XC4000E adders and counters
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2000-06-22 |
| This application note provides formulas for estimating the performance of various adders and counters, which are easily predicted by the XC4000E dedicated carry logic. |
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| Block Adaptive Filter
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2000-06-23 |
| This application note describes a specific design for implementing a high-speed, full precision, adaptive filter in the XC4000E/EX family of FPGAs. |
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| Status and control semaphore registers using partial reconfiguration
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2000-06-29 |
| This application note demonstrates how to lock the LUT SelectRAM to specific locations, determine the corresponding frame of data in the .RBT (Rawbits) file, modify the LUT memory as desired, and re-write this frame into the chip. |
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| Using Select-RAM Memory in XC4000 Series FPGAs
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2000-06-21 |
| This application note describes how to implement Select-RAM memory in XC4000 Series design: in schematic entry, MemGen memory block generator, X-BLOX schematic-based synthesis, and HDL-synthesis environments. It also describes specifying timing requirements, evaluating performance and floorplanning. |
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| Symmetrical 16-Tap FIR filter Macro (FIR16S)
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2000-09-05 |
| This application note details the implementation of a 16-tap FIR Filter Macro in the AT6000 Series FPGAs. |
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| The express configuration of SpartanXL FPGAs
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2000-06-21 |
| This application note provides information on how to perform Express configuration, which uses an 8-bit-wide bus path for fast configuration, specifically for the SpartanXL family of FPGAs. |
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| Second-order IIR digital filter Macro (IIR)
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2000-09-06 |
| This application note details implementation of a second-order IIR digital filter macro in the AT6000 Series FPGAs. |
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| Synthesizable 1.6GBps DDR SDRAM controller
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2001-04-12 |
| This application note describes a 100MHz synthesizable reference controller design for a 64-bit DDR SDRAM. |
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| Performing nibble and dibit switching with the MT90820 (LDX)
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2002-12-04 |
| This application note illustrates the use of the MT90820 as a dibit or nibble switch. |
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| Bus-Structured Serial Input/Output Device
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2000-06-26 |
| This application note discusses how to implement an extensive bus structure by using simple shift registers to illustrate how 3-state busses may be used within an LCA device. |
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