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EE Times Asia - total search 9 articles sort by date sort by relevance
PCIE series Final Inch designs in PCI Express applications generation 1-2.5Gbps 2007-03-12
A single Samtec PCIE Series through hole connector in a board-to-edge card configuration can be used in PCI Express systems with total trace lengths not to exceed 13.9 inches when used with Samtec's Final Inch outing, breakout, and trace width solutions. Because loss is the dominant contributor to system degradation, designers should be aware that using smaller trace widths, laminates with higher loss tangent, and sub optimal routing solutions with higher pair-to-pair coupling and additional via stubs will decrease overall performance and the maximum allowable trace length  
PCIE series Final Inch designs in PCI Express applications Generation 2-5Gbps 2007-04-02
To ensure interoperability between PCI Express transmitter and receiver devices, we will stress a typical interconnect design by stimulating their SPICE model components and devices with stressed data patterns. This paper will cover techniques to stress the system with reduced driver amplitude as well as jitter and noise injection.  
PCIe validation and compliance testing 2011-12-29
Here is an application note intended for digital designers and developers validating electrical performance of PCI Express-based designs and working toward electrical compliance of PCI Express products.  
Powering and configuring Spartan-3 Generation FPGAs in compliant PCI applications 2008-05-26
The information presented in this application note applies to compliant PCI applications using Spartan-3 Generation FPGAs.  
Choose and use high-speed serial data analysis tools 2008-08-01
Serial bus technology raised the bar in performance requirements for high-performance test and measurement instruments used in design, validation and troubleshooting. High data rates are only the initial steps. Designers need better tools to support critical SI measurements and eye diagram analysis.  
Edge Rate ERM8/ERF8 Series 10mm stack height Final Inch designs in PCI Express applications Generation 2—5.0Gbps 2008-06-26
This paper describes a measurement method applied to demonstrate the feasibility of using Samtec Edge Rate ERM8/ERF8 Series connectors with standard FR4 epoxy PCBs.  
Guide to PCB design for CBTL04083A/B 2011-12-06
Here's a practical guideline for PCB design and layout in CBTL04083A/B applications.  
Unbalanced twisted pairs can give you the jitters! 2009-02-17
This application note proposes a new test method for predicting jitter contribution for imbalance (asymmetry) in serial digital-video differential cables. It exposes myths about intrapair skew as a quality indicator and about the misleading relationship between intrapair skew measurement and jitter.  
An SOPC builder PCI Express design with GUI interface 2009-02-25
This application note teaches you how to build an SOPC Builder system that includes a PCI Express MegaCore function and download it to a development board  

EE Times India - total search 554 articles
4Gbps FireWire and its impact on industrial apps 2012-02-13
Targeted design platforms speed 28nm FPGA dev't 2012-02-02
Tilera 64bit chips claim enhanced performance 2012-01-31
Micron acquires storage virtualizer, Virtensys 2012-01-24
Embedded computers target factory automation 2012-01-20
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