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Board and interface design for AutoBahn Spanceiver (MC100SX1451FI50/100
This application note provides detailed information about board design and interface circuits for the AutoBahn Spanceiver |
2000-12-07 |
Design alternatives for the basic user input device interface in portable systems
This paper will investigate the different approaches in the design of the User Input Device Interface, taking into account the unique requirement of UIDs in portable systems, and will point out the advantages and disadvantages of each approach |
1999-10-30 |
Dual DIMM DDR2 SDRAM memory interface design guidelines
As applications become more demanding, deeper memory is required leading to the need for more than one DIMM memory configuration. This application note focuses on the system implementation of a dual unbuffered DIMM DDR2 SDRAM memory interface, operating at 267MHz/533Mbps |
2007-03-05 |
SanDisk CompactFlash & Motorola 8bit microcontroller interface design reference example
The choices and modes for accessing and configuring the SanDisk CompactFlash cards are described in this note. |
1999-10-28 |
V5 access network interface design using MT9075
This application note discusses the use of the V5 interface to either the Access Network or the Local Exchange to enable a network operator to use the access equipment from any vendor conforming the V5 interface specifications |
1999-10-19 |
CompactFlash and 8260 interface design guide
This application note describes a possible interface between a CompactFlash card and Motorola's MPC8260 microprocessor |
2002-05-09 |
ACCEL-To-SPECCTRA interface and design language translation
This application note describes the background involving the interface between ACCEL EDA and Specctra |
2001-05-28 |
ISP1581 USB 2.0 Scanner using ASIC from Service & Quality Technology Co. Ltd
This application note provides details on how to implement the USB 2.0 scanner design using the ISP1581 high-speed USB 2.0 interface device together with the SQ009 ASIC from Service & Quality Technology |
2003-05-27 |
Configuring Virtex FPGAs from Parallel EPROMs with a CPLD
This application note describes a simple interface design to configure a Virtex device from a parallel EPROM using the SelectMAP configuration mode |
2000-06-23 |
Designing a DSP system
This application note describes various aspects of DSP system design such as interfacing A/D and D/A converters, DAQ techniques (Busy-Polling, Interrupts, DMA), control interface design, memory considerations, and development systems |
2001-10-12 |
IOM-2 interfacing on TMS320C54x
This application note describes an interface design for connecting the synchronous serial port of Texas Instruments' TMS320C54x DSP to an IOM-2 serial bus |
2001-04-30 |
Improving memory access timing in Z182 applications
This application note demonstrates the calculations of both ROM and RAM access timing, provides examples of a conventional processor/memory interface design, and presents an alternate approach to processor/memory design |
2000-09-08 |
The TMS320C54x DSP HPI and PC parallel port interface
This application note describes the hardware interface design between the host (PC parallel port in the bi-directional mode) and the HPI (host port interface) using TI's TMS320C54x DSP |
2001-05-02 |
Single Ended and Single Power Supply Hybrid Circuit
This application note introduces a simple hybrid circuit that will save costs as well as provide high performance in power supply interface design. It highlights transmission and reception features along with PCB guidelines and details on parameters such as output level |
2000-04-13 |
High-speed ADC THS1041and FPGA interface considerations
The THS1041 from Texas Instruments is a 10bit, 40MSPS, high-speed ADC. For many years because of its low power dissipation and extended life, it has been used in various applications such as programmable gain amplifier and built-in clamp. With recent FPGA development, some application systems have been upgraded with a direct interface of the THS1041 to an FPGA, for example, by connecting I/O pins of the THS1041 to the I/O pins of Xilinx Spartan-3 or Altera PLD. For such an interface, a power-on initial state should be considered in the interface design. Otherwise, the power-on initial state of the FPGA can affect the initial state of THS1041 and in some cases, affect the entire application system. In order to ensure the successful interfacing of the THS1041 to an FPGA, a test was conducted, and this application report presents those results |
2007-05-04 |
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