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2010-05-21 What is formal verification?
Functional verification is a critical element in the development of today's complex digital designs. Hardware complexity growth continues to follow Moore's Law, but verification complexity is even more challenging
2003-07-30 Verplex upgrades formal-verification line
On the verge of closing its sale to Cadence, Verplex is releasing an upgrade to its Conformal line of equivalence checkers.
2011-05-25 Verification tool quantifies verification progress
OneSpin launched its first comprehensive automatic metric-driven solution that analyzes and measures formal verification progress and quality in register transfer level (RTL) designs.
2009-01-21 Verification tool provides step-by-step approach
OneSpin Solutions has amended its software and packaged it in a way that supports a step-by-step approach for beginners.
2002-03-11 Verification tool enables rapid ASIC prototyping
Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification environment addresses all hardware prototype creation and verification challenges
2002-08-26 TransEDA offers PCI-X 2.0 verification IP
TransEDA PLC has put together a new verification bundle for designers wishing to create SoCs compliant with the PCI-X 2.0 standard
2002-04-22 TransEDA licenses formal-verification technology from SRI
Making a concerted effort to be seen as more than a simulation add-on tool vendor, TransEDA plc has licensed raw formal-verification technology from Stanford Research Institute and plans to turn this know-how into formal and semiformal verification tools within a year.
2010-06-08 Tools offer shared database for design, verification
From Jasper Design Automation come improved versions of the ActiveDesign and JasperGold tools with capabilities that bridge the divide between chip design and verification by sharing common database
2007-03-16 Take distinctive approach to IC verification
Richard Goering spoke with Hooman Moshar about Broadcom's distinctive approach to IC verification
2007-09-20 Taiwan's MediaTek adopts Mentor's formal verification tech
Mentor Graphics announced that Taiwan's MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects.
2014-03-07 Synopsys unveils verification compiler sol'n
The Verification Compiler is a portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure.
2003-06-27 Synopsys strengthens verification efforts with acquisition
Synopsys Inc. has acquired InnoLogic Systems Inc., a provider of memory and full-custom equivalence checking technology.
2003-01-21 Synopsys moves customers to verification area
Synopsys Inc. hopes to hold on to a slight lead in the formal verification market as it moves customers from the Design Verifyer tool to its internally developed Formality equivalence checker.
2002-10-15 Swedish startup eases use of formal tools
Startup Safelogic is rolling out a formal property checker and a simulation "plug-in" for property monitoring
2005-10-27 Survey finds verification tool use largely unchanged from 2004
The 2005
2007-06-14 Simulink design suite adds formal methods
Adding formal design methods to its widely used Simulink model-based design suite, The Mathworks Inc. has introduced the Simulink Design Verifier, which generates tests and proves properties for models from the company's Simulink simulation platform and Stateflow design and simulation tool
2008-02-26 Rhines on EDA: End 'endless verification
Walden Rhines of Mentor Graphics calls for a combination of formal methods, TLM techniques and intelligent testbenches to lower the cost of design verification.
2002-04-15 Researchers propose dual design verification model
Indian researchers are proposing a novel verification methodology that uses two representations of a design throughout the verification process, one a behavioral model in C and the other an RTL model
2005-03-28 Renesas integrates Mentor's 0-In for assertion based verification flow
Renesas Technology Corp. has completed the integration of Mentor Graphics Corp.'s 0-In assertion synthesis technology and assertion-based verification flows with Renesas' LogicBench rapid prototyping system
2006-08-18 Realtek, Cadence collaborate on formal verification design
Cadence Design and Realtek Semiconductor announced that they have collaborated to successfully reduce the risk of functional errors on its pilot multi-supply voltage design.
2002-05-30 Real Intent brings clock checking to formal tool
Real Intent Corp. has added what it terms formal clock intent verification to its Verix assertion-driven formal verification tool.
2010-12-17 Proof kits enable faster, accurate SoC verification
Jasper Intelligent Proof Kits encapsulate critical behaviors for popular protocols such as ARM’s AMBA, allowing users to quickly configure designs to the standard or adapt them to their own custom configuration. These kits are optimized for high-level verification with Jasper’s ActiveDesign and JasperGold formal verification.
2003-07-03 PLX, Jasper partner on formal verification solution
PLX Technology Inc. and Jasper Design Automation have collaborated to bring formal verification to PLX chips based on PCI Express technology, via the JasperGold formal verification tool.
2002-11-18 Plugging the verification time sink
Logic equivalence checking provides an independent means of verifying the design process and reduces the overall verification effort
2004-12-01 Methodology sought for assertion-based verification
Silicon IP providers and creators seek guidelines on how to use assertions effectively, aside from the standard protocols.
2003-03-05 Mentor Graphics to develop FPGA verification solution for Thales
Mentor Graphics Corp. has entered into a technology relationship with Xilinx Inc. and Thales Communications to develop a new FPGA verification flow to meet Thales' requirements for its next-generation products
2003-06-16 Memory verification needs fresh approach
By interpreting parameter values corresponding to the implementation structure, equivalence-checking comparisons between RT and transistor level can be easily accomplished.
2004-06-01 Jasper upgrades verification product
Jasper has announced its JasperGold product that enables what the company calls a "provably correct design" methodology.
2004-05-06 Jasper upgrades verification product
Jasper Design Automation will announce the latest release of its JasperGold product enabling what the company calls a provably correct design methodology.
2004-07-01 Jasper upgrades verification product
The company has announced the latest JasperGold product enabling what Jasper calls a "provably correct design" methodology.
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