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2010-05-21 What is formal verification?
Functional verification is a critical element in the development of today's complex digital designs. Hardware complexity growth continues to follow Moore's Law, but verification complexity is even more challenging
2003-07-30 Verplex upgrades formal-verification line
On the verge of closing its sale to Cadence, Verplex is releasing an upgrade to its Conformal line of equivalence checkers.
2011-05-25 Verification tool quantifies verification progress
OneSpin launched its first comprehensive automatic metric-driven solution that analyzes and measures formal verification progress and quality in register transfer level (RTL) designs.
2002-03-11 Verification tool enables rapid ASIC prototyping
Designed for creating ASIC and SoC prototypes using off-the-shelf FPGAs, the SpeedGate Direct System Verification environment addresses all hardware prototype creation and verification challenges
2002-04-22 TransEDA licenses formal-verification technology from SRI
Making a concerted effort to be seen as more than a simulation add-on tool vendor, TransEDA plc has licensed raw formal-verification technology from Stanford Research Institute and plans to turn this know-how into formal and semiformal verification tools within a year.
2010-06-08 Tools offer shared database for design, verification
From Jasper Design Automation come improved versions of the ActiveDesign and JasperGold tools with capabilities that bridge the divide between chip design and verification by sharing common database
2007-09-20 Taiwan's MediaTek adopts Mentor's formal verification tech
Mentor Graphics announced that Taiwan's MediaTek has selected the 0-In formal verification technology to make it an integral part of its verification flow for their next generation design projects.
2014-03-07 Synopsys unveils verification compiler sol'n
The Verification Compiler is a portfolio of integrated, next-generation verification technologies that include advanced debug, static and formal verification, simulation, verification IP and coverage closure.
2003-06-27 Synopsys strengthens verification efforts with acquisition
Synopsys Inc. has acquired InnoLogic Systems Inc., a provider of memory and full-custom equivalence checking technology.
2003-01-21 Synopsys moves customers to verification area
Synopsys Inc. hopes to hold on to a slight lead in the formal verification market as it moves customers from the Design Verifyer tool to its internally developed Formality equivalence checker.
2005-10-27 Survey finds verification tool use largely unchanged from 2004
The 2005
2006-08-18 Realtek, Cadence collaborate on formal verification design
Cadence Design and Realtek Semiconductor announced that they have collaborated to successfully reduce the risk of functional errors on its pilot multi-supply voltage design.
2002-05-30 Real Intent brings clock checking to formal tool
Real Intent Corp. has added what it terms formal clock intent verification to its Verix assertion-driven formal verification tool.
2010-12-17 Proof kits enable faster, accurate SoC verification
Jasper Intelligent Proof Kits encapsulate critical behaviors for popular protocols such as ARM’s AMBA, allowing users to quickly configure designs to the standard or adapt them to their own custom configuration. These kits are optimized for high-level verification with Jasper’s ActiveDesign and JasperGold formal verification.
2003-07-03 PLX, Jasper partner on formal verification solution
PLX Technology Inc. and Jasper Design Automation have collaborated to bring formal verification to PLX chips based on PCI Express technology, via the JasperGold formal verification tool.
2004-06-01 Jasper upgrades verification product
Jasper has announced its JasperGold product that enables what the company calls a "provably correct design" methodology.
2004-07-01 Jasper upgrades verification product
The company has announced the latest JasperGold product enabling what Jasper calls a "provably correct design" methodology.
2002-11-21 IBM offers free trial of assertion-based verification tool
IBM's Haifa Research Laboratory has started to offer the company's FoCs assertion-based verification tool for a free 90-day trial
2002-03-01 Functional verification of 10M-gate SoCs
This technical article discusses the advantages of implementing the "white-box" design methodology for instrumenting RTL structures inside very large SoC designs as compared to the traditional black-box test suites.
2006-07-26 Formal verification tool promises finer control
Averant released the next generation of its formal verification tool, offering what the company claims is the industry's first formal tool to give designers fine control over the tool's thoroughness.
2001-06-01 Formal verification of an MPEG decoder chip
This article outlines the application of formal verification through model checking of the control unit in a DVD decoder chip.
2003-11-17 Formal verification for IP soft core
Engineers are facing challenges on improving design efficiency and shortening time-to-market of IP soft core--formal verification is believed to provide a new solution for them.
2007-09-17 Formal verification fetches better results
Complete formal verification is not a silver bullet for all functional verification tasks. But for a broad range of digital modules and IP, it delivers far superior results in terms of verification quality, effort and costs.
2000-09-01 Formal verification by equivalence checking in deep sub-micron designs
Equivalence verification tools compare the logical behavior of two circuits while ensuring a consistent design flow. They aim to combine structural checking with handling of multi-million gate designs in a small memory footprint
2003-06-10 Formal tools won't replace simulation
Formal verification is a valuable adjunct to simulation, but not a replacement for it, according to panelists at the Design Automation Conference.
2010-02-19 Dealing with formal verification constraints
Formal model checkers are indispensable, complementing simulation for block-level verification in an ever-challenging design environment. Constraints make a formal tool tick.
2006-06-01 Breaking the verification barrier
Startup OneSpin Solutions believes it has technology that will usher in a new era of IC formal verification. But if this company is successful, the real breakthrough may be one of bringing internal technology from a large integrated device manufacturer into a global, commercial EDA market.
2006-09-18 Averant dives deep into formal verification
Averant took advantage of Design Automation Conference to roll out the next generation of its Solidify tool, offering designers fine control over the thoroughness of formal verification.
2008-09-01 Automate formal verification for OCP
The automation of formal protocol verification using VIPs enables a rapid and exhaustive verification of critical IP interfaces. Once a VIP library is written and tested, it can be re-used to improve the verification quality and shorten the verification schedule. VIPs can also be used to ease the verification of high-level system properties since they provide a "free" environment.
2002-01-10 Aldec rolls out fast, fully automated FPGA design verification tool
Claimed to be the fastest, most fully automated FPGA design verification tool, Active-HDL 5.1 addresses the latest design trends in the EDA industry, the company says
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